Self-aligned fabrication method for ridge-waveguide...

Details Self-aligned fabrication method for ridge-waveguide... Self-aligned fabrication method for ridge-waveguide...

2002-05-07

2003-01-07

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making device or circuit emissive of nonelectrical signal

C438S042000

Reexamination Certificate

active

06503770

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the invention
The present invention relates to the fabrication of a semiconductor laser, and in particular, a self-aligned fabrication method for ridge-waveguide semiconductor laser.
2. Description of the Prior Art
Referring to FIG.
1
A and
FIG. 1B
, in which two conventional structures of a ridge-waveguide semiconductor laser arc shown. Both the epitaxial structures consist of a semiconductor substrate
100
(such as N-type semiconductor substrate), a first semiconductor waveguide layer
101
, a first semiconductor confinement layer
102
, a semiconductor active layer region
103
, a second semiconductor confinement layer
104
, a second semiconductor waveguide layer
105
, and a semiconductor ohmic contact layer
106
. And, a dielectric passivation layer
107
a
or
107
b
, a P-type metal electrode
108
a
or
108
b
, and a N-type metal electrode
109
are comprised in both structures.
The fabrication of both structures starts with pattern definition through standard photolithography process, followed by an etching process such as reactive-ion etching (RIE) to form a semiconductor ridge along with a double trench structure
110
shown in
FIGS. 1A and 1B
. The dielectric layer
107
a
or
107
b
is then deposited on the entire wafer surface to provide semiconductor surface passivation. After a contact window on the ridge top is formed to expose the ohmic contact layer
106
, the P-type metal electrode
108
a
or
108
b
is formed so as to make contact with the semiconductor contact layer
106
. Finally, the N-type metal electrode
109
is formed underneath the wafer after the wafer has been lapped and polished.
To reduce the threshold current for lasing action and to maintain single-transverse mode operation, the ridge width W is usually limited to about 2 &mgr;m. Such a narrow ridge causes problems when a contact window is to be opened on top of it to expose the ohmic contact layer
106
. The most direct way is to define the contact window
106
on the ridge top through mask alignment and photolithography process as shown in FIG.
1
A. However, the defined contact window should be narrower, a rather accurate mask alignment is required. Besides, even by doing so, the aim of perfect utilization of the ohmic contact layer
106
is hard to attain resulting in an non-optimized contact between metal and semiconductor.
In view of the above description, it emerges a fact that the semiconductor laser fabricated according to conventional techniques has by no means an acceptable quality.
A number of alternative methods were proposed to expose the semiconductor contact layer of the ridge top more conveniently and to fully utilize the ridge top for metal contact, such as U.S. Pat. No. 4,830,986, U.S. Pat. No. 5,059,552, U.S. Pat. No. 5,208,183, U.S. Pat. No. 5,474,954, U.S. Pat. No. 5,504,768, U.S. Pat. No. 5,258,823, and U.S. Pat. No. 6,171,876. In U.S. Pat. No. 5,504,768, a P-type metal stripe defining a semiconductor ridge structure region was deposited onto the wafer surface at the beginning of the process and then served as the mask for semiconductor ridge etching, therefore ensured that the ridge top was fully contacted. However, in the successive process, a stringent mask-aligning process is required for overlaying metal to precisely connect the P-type metal stripe and the bondpad.
In other patented cases, a self-alignment concept was introduced and methods for implementing this concept can be classified into two categories, and both will lead to a typical device structure depicted in
FIG. 1B
, in which the whole ridge top is fully utilized for metal contact. In the first kind, such as in U.S. Pat. No. 4,830,986 and U.S. Pat. No. 5,059,552, a photoresist mask was used to define and form a semiconductor ridge. This photoresist mask on the ridge top was preserved until the entire wafer surface was covered with an insulating dielectric film, such as silicon oxide (SiOx) or silicon nitride (SiNx). Then the photoresist mask was chemically removed by (acetone, for instance) and the ohmic contact layer on the ridge top was revealed without exposing other semiconductor surfaces out of the dielectric film. This scheme is called “self-alignment” by reason that exposing of the ohmic contact layer does not require processes of mask aligning and photolithography. Although such a scheme can attain the aims of simplifying the fabricating process and full utilization of the ohmic contact layer. Preservation of the photoresist mask necessitates low temperature (100° C.) dielectric layer deposition which causes degradation of the quality of the dielectric layer. Besides, a suitable undercut profile of the semiconductor top ridge is required to facilitate photoresist mask's removal after deposition of the dielectric layer, and this complicates the process.
In the second kind, such as U.S. Pat. No. 5,208,183, U.S. Pat. No. 5,474,954, U.S. Pat. No. 5,658,823, and U.S. Pat. No. 6,171,876, the planarization capability of the photoresist or polyimide was utilized. As photoresist or polyimide is spun onto the ridge structured wafer surface, the flowing nature results in a profile that has a much thinner resist or polyimide on the ridge top than on the rest of the wafer surface. By overall etch-back process, such as RIE, the semiconductor ridge top can be revealed at first without exposing other semiconductor surfaces. Therefore the entire ridge top can be fully utilized for metal contact. The difference between using photoresist and polyimide is that after exposing the ridge top, the polyimide layer is left on the wafer surface and serves as a dielectric planarization layer. The P-metal with its bondpad is then directly formed thereon. Therefore using the polyimide will be a more straightforward method. Besides, a single-ridge structure can be adopted for forming the ridge-waveguide semiconductor laser by planarization of the polyimide. By so the metal coverage problem usually encountered in double-trench structure can be avoided.
However, the polyimide film, even cured, still retains flexible property. During facet cleavage process, elongated polyimide film in the edge might interfere with the laser output surface and affect the structural property and uniformity.
Aiming at the above depicted defects, the present invention is to propose a newly developed self-aligned fabrication method for ridge-waveguide semiconductor laser capable of eliminating existing defects.
SUMMARY OF THE INVENTION
The present invention teaches a self-aligned fabrication method for ridge-waveguide semiconductor laser. This method can be applied by performing what is called “self-terminated oxide polish, abbreviated as STOP” technique followed by deposition of a thick oxide layer. Taking SiOx for example, this thick oxide layer (thicker than the ridge height) covers the entire wafer surface. The oxide corrugations due to deposition on the ridge-structured wafer surface are then polished down to a flat plane. The polishing process removes the narrow oxide ridge (narrower than 10 &mgr;m for instance) rapidly, while almost halts when the oxide surface is flattened. Such behavior finally results in a rather flat oxide plane. The planarity therefore depends on the oxide deposition mechanism rather than on the polishing process.
For achieving the object of the self-aligned fabrication method for ridge-waveguide semiconductor laser described above. The present invention utilizes a process of planarizing a dielectric layer in which a dielectric layer of sufficient thickness is covered over a ridge-structured semiconductor wafer surface, the oxide corrugations formed on the surface of the dielectric layer is then polished down to a flat plane by the STOP technique, and followed by over-all etch-back process for this planar dielectric layer, the ridge tops of the semiconductor laser can be exposed uniformly.


REFERENCES:
patent: 4830986 (1989-05-01), Plumb
patent: 5059552 (1991-10-01), Harder et al.
patent: 5208183 (1993-05-01), Chen et al.
patent: 5474954 (1995-12-01), Yang
patent: 5504768

Affiliated with

Also associated with

Rating

Self-aligned fabrication method for ridge-waveguide... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Self-aligned fabrication method for ridge-waveguide..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Self-aligned fabrication method for ridge-waveguide... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3005486