Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-07-13
2003-01-07
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06505325
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a pattern data density inspection apparatus for inspecting the density of mask layout data in a pattern layout for a semiconductor device.
2. Background Art
Recently, with the progress in miniaturization of semiconductor devices, tolerances in dimensional accuracy of the layout design, that is to say, manufacturing error tolerances such as in the width and pitch of the line pattern, in the contrast, and in the dimensions in the height direction have become small so that if there is not sufficient flatness in the interlayer insulation film between multilayer wiring, manufacture of the semiconductor device becomes impossible. That is to say, as shown in
FIG. 6
, the surface of an interlayer insulation film I
1
on an upper portion of a wiring pattern P
1
formed on a substrate S surface, is formed naturally higher than other regions. In the case where a next layer wiring pattern is formed on the surface of this interlayer insulation film I
1
, reliability is impaired due for example to the wiring pattern of the next layer becoming severe at a step portion E
1
of the interlayer insulation film I
1
, and the width of the pattern wiring being formed narrow, so that with the passing of time, this narrow portion becomes disconnected by electro-migration.
Furthermore, the surface shape of the interlayer insulation film formed on the upper portion of the pattern wiring, changes due to the value of the wiring width. As shown in
FIG. 7
, a step E
2
of an interlayer insulation I
2
, formed on the substrate S surface, compared to the step E
1
shown in
FIG. 6
, has a restrictive shape with respect to formation of the next wiring pattern. Therefore, in order to prevent the occurrence of the above mentioned disconnection and the like of the wiring pattern of the next layer and the upper layer, a planarization technique for the interlayer insulation film involving CMP (Chemical Mechanical Polishing) or the like is used. Here,
FIG. 6
(and
FIG. 7
) are sectional views of a semiconductor device showing a configuration example of an interlayer insulation film I
1
(interlayer insulation film I
2
) formed when a pattern P
1
(pattern P
2
) is on the bottom layer.
However, with the above mentioned planarization technique, the interlayer insulation film cannot be completely planarized. That is, as shown in
FIG. 8
, in the case where the width of the wiring pattern P
1
is narrow, the difference in level is removed. However, in the case where the width of the wiring pattern P
2
is wide, a small difference in level remains This difference in level is referred to as a global difference. Therefore, while with the dimensional accuracy in the layout design of conventional semiconductor devices, it is possible to cope with the remaining global difference, with the progress of miniaturization, this remaining difference in level has become a shape having a height which cannot be disregarded. Here, a distance between the surface of an interlayer insulation film I
3
on an upper portion of the wiring pattern P
2
, and the surface of an interlayer insulation film I
3
on an upper portion of the substrate S, that is to say the height of the global difference, is made dg. Here
FIG. 8
is a sectional view of a semiconductor device showing a configuration example of an interlayer insulation film I
3
which is formed when a pattern P
1
, a pattern P
2
and a pattern P
3
are the lower layer.
For example, as shown in
FIG. 8
, in the case where the wide wiring patterns P
2
and P
3
are formed adjacent, the interlayer insulation film I
3
is formed with a skirt with a difference in level, on the upper portion of the wiring pattern P
2
and the wiring pattern P
3
. Hence this is formed with a thickness including the height of the global difference, on the surface of the substrate S between the wiring pattern P
2
and the wiring pattern P
3
. Consequently, the thickness of the interlayer insulation film for the substrate surface becomes non uniform.
Therefore, the etching depth in the interlayer insulation film I
3
, for a contact hole CT
1
for a dispersion layer D
1
formed on the substrate S surface, and a contact hole CT
2
for a dispersion layer D
2
formed on the substrate S surface differs. That is to say, when the contact hole CT
2
reaches the surface of the dispersion layer D
2
, the contact hole CT
1
has not yet reached the surface of the dispersion layer D
1
.
Consequently, in the case where the etching of the interlayer insulation film I
3
is continued so that the contact hole CT
1
reaches to the dispersion layer D
1
, over etching occurs with respect to the contact hole CT
2
. As a result, the contact hole CT
2
reaches the dispersion layer D
2
surface and the dispersion layer D
2
surface is then etched. Hence lattice defects occur bringing about a deterioration in electrical characteristics such as a drop in the breakdown resistance of the dispersion layer D
2
.
Since as mentioned above there is a limit to the planarization technique, it has been considered in the stage for layout design of the semiconductor memory device, to detect congested regions (pattern data density error regions) with wide wiring patterns which produce this global difference, to thus prevent the occurrence of global differences. For example the graph shown in
FIG. 9
shows the experimentally obtained relationship between the width (X axis) of isolated aluminum wiring as a wiring pattern, and the height dg (Y axis) of the global difference. The change in global difference shown in the figure for an aluminum wiring width near 400 &mgr;m is large. Moreover, if the height is around this height dg, this can be permitted. At this time, in the design rule used for making the graph of
FIG. 9
, the thickness of the aluminum wiring is 600 nm, and the thickness of the interlayer insulation film is 800 nm.
Furthermore, in the region of a 400 &mgr;m square (400 &mgr;m×400 &mgr;m), if the area density of the aluminum wiring (the value for the total surface area of the aluminum wiring pattern divided by the area of the region; the pattern data density) becomes greater than 50%, it is confirmed experimentally that the condition is equivalent to the change in global difference for an aluminum wiring width near 400 &mgr;m. Furthermore, it is similarly obtained by experiment that when obtaining this area density, aluminum wiring where the wiring width is less than 1.2 &mgr;m can be ignored. Based on this result, a chip of a semiconductor device is divided into lattice shape detection regions and the pattern data density in each of the detection regions obtained. Then with a detection range where this pattern data density exceeds 50% as a pattern data density error region, a designer of a layout pattern considers processes to prevent the occurrence of global differences to obtain correction of the wiring pattern. Hereunder is a description of the process for detecting pattern data density error regions.
A description is given of a conventional pattern data density inspection apparatus based on the figures.
FIG. 10
is a block diagram showing the construction of a conventional pattern data density inspection apparatus. A control section
100
reads out layout data for performing inspection, from a layout storage section
101
in which is stored a plurality of layout data, and writes the read out layout data to an input processing section
102
and an output processing section
104
, where this is stored. This layout data is wiring pattern data, that is to say a wiring layer data file.
A density computation processing section
103
, under instructions from the control section
100
, divides the layout data stored in the input processing section
102
into lattice shape detection ranges, and performs pattern data density computations for each of the detection ranges. Furthermore, the density computation processing section
103
judges if the pattern data density for each of the detection ranges is above 50%. At this time, the density computat
Choate Hall & Stewart
Levin Naum
NEC Corporation
Smith Matthew
LandOfFree
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