Self-aligned fabrication method for a semiconductor device

Details Self-aligned fabrication method for a semiconductor device Self-aligned fabrication method for a semiconductor device

2001-10-19

2003-11-11

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

Having heterojunction

C117S090000

Reexamination Certificate

active

06645819

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing semiconductor devices using a self-aligned fabrication process.
2. Background
Fabrication of an integrated circuit (“IC”) comprises a sequence of processing steps to produce electrical devices contained in a semiconductor chip. During the production of ICs, various layers of thin films of dielectrics (e.g., SiO
2
, Si
3
N
4
, etc.), polysilicon and metal conductors (e.g., Al, Ni, Au, Pt, Ti, etc.) are grown or deposited on the surface of a semiconductor wafer (“wafer”), one on top of the other.
Deposition is an operation in which a film is placed on the wafer surface, usually without a chemical reaction with the underlying layer. Deposition is also known as “evaporation”. Two common techniques used for forming these thin films are physical vapor deposition and chemical vapor deposition. Chemical vapor deposition is a process in which insulating or conducting films are deposited on a substrate by use of reactant gasses and an energy source to produce a gas-phase chemical reaction. The energy source may be thermal, optical or plasma in nature. Physical vapor deposition is a process in which a conductive or insulting film is deposited on a wafer surface without the assistance of a chemical reaction. Examples of physical vapor deposition include vacuum evaporation and sputtering.
To perform its intended function, each deposited layer must be located within a specific region on the wafer surface. This is accomplished by forming a desired layer and then patterning and etching it to provide a certain device function in specific areas of the wafer. Often a mask is used in this patterning and etching process. Lithography is a transfer process where the pattern on the mask is replicated in a radiation-sensitive layer located below the mask on the wafer surface. Typically, this has been accomplished with UV light as the radiation source and photo-resist (“resist”), which is a UV-sensitive polymer, as the mask layer. First, a few drops of resist are deposited on a wafer which is spinning at a slow rate to produce a uniform coating and the spin speed is increased to enhance drying. The wafer with resist is softbaked at 80-90° Centigrade for 10-30 minutes to drive off the remaining solvents. Next, the wafers are put in an exposure system and the mask pattern to be transferred is aligned to any existing wafer patterns. The resist is exposed through the mask to UV radiation that changes its structure, depending upon whether the resist type is positive or negative. For a positive type resist, the resist dissipates when exposed to light and a subsequent solvent application. In contrast, the negative type resist hardens after exposure to light and is not removed by the subsequent solvent application. The resist is not affected in regions where the mask is opaque in either case. After full wafer exposure the resist is developed such that the unpolymerized regions are selectively dissolved in an appropriate solvent. The polymerized portion of the resist remains intact on the wafer surface reflecting the opaque features of the mask in a positive resist and just the opposite for a negative resist.
After the resist pattern is formed it is then transferred to the surface layer of the wafer. Sometimes this is an invisible layer, such as ion implantation, but more often than not it is a physical transfer of the pattern by etching the surface layer, using the resist as a mask. This either results in the desired structure or produces a more etch-resistant mask for further pattern transfer operations.
Two common types of etching processes used in semiconductor fabrication include wet etching and dry etching. Wet etching is a process which uses liquid chemical reactions with unprotected regions of a wafer to remove specific layers of the substrate. During wet etching, wafers with resist (or a resist transferred mask) are immersed in a temperature-controlled etchant for a fixed period of time. The etch rate is dependent on the strength of the etchant, temperature and material being etched. Such chemical etches are isotopic, which means that the vertical and lateral etch rates are the same. Thus, the thicker the layer being etched, the more undercutting of the mask pattern. Most wet etches are stopped with an underlying etchstop layer that is impervious to the etchant used to remove the top layer.
Dry etching is also used during semiconductor fabrication. Dry etching is a process that uses gas-phase reactants, inert or active ionic species or a combination of these techniques to remove unprotected layers of a substrate by chemical and/or physical processes. Unlike wet etching, dry etching is an anisotropic etching process, such that the etch rate may be varied in different directions. One common dry etching technique is called plasma etching, which uses a rf plasma to generate chemically active etchants that form volatile etch species with the substrate. In plasma etching, a wafer is placed between two plates and a voltage is applied to the plates that ionizes gases in between the plates to accomplish the etching. Typically, chlorine or fluorine compounds, most notably CCl
4
and CF
4
, have been tailored for etching SiO
2
, Si
3
N
4
and metal layers. Another example of dry etching is known as ion etching. Ion etching is accomplished using an inactive species (e.g., Ar ions) either in a beam or with a parallel plate sputtering system.
In a semiconductor device, two different layers may be electrically connected together using a contact, usually made of metal. The fabrication process of the contact depends on the type of layers that are to be connected. Two common techniques used for evaporating metals are physical vapor deposition and chemical vapor deposition, as discussed above.
One common type of semiconductor device is called a transistor. Typically, ICs often comprises many thousands or millions of transistors as building blocks for various electrical circuits. Transistors are comprised of an emitter layer, a collector layer and a base layer. Transistors often act as switches by controlling a primary current flow from the collector to the emitter. A much smaller secondary current is applied to the base to control the primary current.
One type of transistor used in ICs is known as a heterojunction bipolar transistor, or “HBT”. HBTs are designed by varying the band-gap energy levels of the emitter and base layers in order to maximize performance. HBTs are used in many applications, such as in semiconductor chips used for communication systems including optical components, wireless power amplifiers for cell phones and base stations, low noise amplifiers and high performance analog to digital converters.
When considering construction of an HBT, the base to emitter separation distance is important for the reliability and high frequency performance of the device. For example, improper production of the base-emitter separation may effect the yield loss of the wafers during the manufacturing process. In addition, the mean time for failure (“MTTF”), which is a measure of the reliability of the HBT under typical operating conditions, depends on the base-emitter separation and the properties of the dielectric layer that passivates the base-emitter interface. Further, because a significant part of the base resistance in the HBT is directly proportional to the base-emitter separation, a greater separation provides a higher base resistance, resulting in a degradation of the power gain of the HBT at high frequencies. Accordingly, high frequency performance is improved by providing a base-emitter separation that is as small as possible.
One conventional process of manufacturing a HBT is known as a self-aligned fabrication process. This fabrication process is considered “self-aligned” because the base-emitter separation is not defined by lithography. Rather, the base-emitter separation is defined by the shape of the elements in the transistor, specifically, by the shape of an overhang of the emitter over th

Affiliated with

Also associated with

Rating

Self-aligned fabrication method for a semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Self-aligned fabrication method for a semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Self-aligned fabrication method for a semiconductor device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3168744