Self-aligned emitter and base BJT process and structure

Details Self-aligned emitter and base BJT process and structure Self-aligned emitter and base BJT process and structure

1998-05-18

2001-01-23

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

Having heterojunction

C438S309000, C438S364000

Reexamination Certificate

active

06177325

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor devices. In particular, the invention relates to a self-aligned bipolar junction transistor and a method for forming the same.
BACKGROUND OF THE INVENTION
A conventional bipolar junction transistor
10
is depicted in FIG.
1
. The device is formed on a silicon substrate
12
which is illustratively P
−
type. A buried N
+
layer
14
is located on the substrate
12
and an N-type collector region
16
is located on buried N
+
layer
14
. In addition, a plurality of field oxide (FOX) regions
18
are formed on the substrate. An N
+
deep connection region
20
connects the substrate surface to the buried N
+
layer
14
to form a collector contact to collector
16
. A P-type base region
22
is formed in the N-type well
16
, which forms the collector. Two P
+
-type base contact regions
24
and
26
are formed on either side of the base
22
.
The emitter
28
includes the N
+
polysilicon or polycide region
30
formed on the surface of the substrate. The emitter
28
also includes the N diffusion region
29
. Spacers, such as oxide spacers
32
and
34
, are located on either side of the N
+
polysilicon region
30
. Two metal contacts
36
and
38
connect to the P
+
base contact regions
24
and
26
. A third metal contact
40
connects to the deep connector region
20
for contact with the N
+
collector buried layer
14
. A fourth metal contact
41
connects the surface to the emitter
28
. Note that metal contacts
36
,
38
,
40
and
41
are formed in openings of an inter-layer-dielectric (ILD) layer
42
.
The overall structure is an NPN transistor with N-type collector
16
, P-type base
22
and N-type emitter
28
. The buried N
+
layer
14
and N
+
deep connector
20
form a collector contact, whereas the P
+
regions
24
and
26
form a base contact. Because the base contact regions do not connect directly to the P-type base regions
22
, there is a parasitic resistor R
b
in series with the base of the BJT. The value of R
b
is determined by the P
+
diffusion sheet resistance and the distance L
1
between the base contact and the emitter. In general, P
+
diffusion sheet resistance cannot be improved significantly without affecting device characteristics. The distance L
1
depends on photo alignment tolerance between the polysilicon emitter and contact, and the metal contact process. Therefore R
b
can be reduced if L
1
is shortened. However, a distance L
2
is also needed to prevent contact of base metal regions
36
and
38
to the isolation regions, e.g. field oxide regions
18
. The existence of L
1
and L
2
and the base contacts will enlarge the P
+
diffusion regions
24
and
26
(to a depth of 0.3 &mgr;m and a width of 1.4 &mgr;m). Therefore, there exists a large base to collector capacitance C
bc
. Capacitance C
bc
will degrade BJT device performance greatly since it is located between the input node and the output node in the CE (common emitter) configuration of the BJT.
To improve the BJT characteristics, a first proposed BJT
10
′ with a self-aligned base contact is formed using a process as depicted in FIG.
2
. Using conventional front end processes, the N
+
layer
14
is formed on the substrate
12
. Further, the N-type collector region
16
is formed and then the field oxide (FOX) regions
18
are formed on the substrate surface. The deep collector connector region
20
is then formed by diffusion or ion implantation into the N-type well
16
. Next, the P base region
22
is formed by diffusion or ion implantation. Thereafter, the P
+
polysilicon interconnect links
54
and
56
are formed. Specifically, the interconnect links
54
and
56
are formed by depositing a polysilicon layer, patterning the polysilicon layer using photolithography and then etching. The P
+
base contact regions
24
and
26
are formed by out-diffusion from the P
+
polysilicon interconnect links
54
and
56
. This forms a self-aligned link from the P base
22
, through the P
+
base contact regions
24
and
26
, and through the P
+
polysilicon regions
54
and
56
to the base metal contacts
36
and
38
(which are formed after ILD deposition).
Next the emitter
28
is formed by depositing an N
+
polysilicon layer and patterning this layer to form the N
+
polysilicon emitter region
30
. The N
+
emitter region
29
is formed by out-diffusion from the N
+
polysilicon region
30
. After this, the ILD layer
42
is formed and patterned to enable formation of the metal contacts
36
,
38
,
40
and
41
.
From these steps the BJT
10
′ with the self aligned base contact is formed. Because the P base
22
is connected using the P
+
polysilicon regions
54
and
56
, the P
+
base contact regions
24
and
26
can be made smaller than the P
+
base contact regions in the conventional device of FIG.
1
. Thus, the collector-base capacitance C
bc
in the device
10
′ of
FIG. 2
is smaller than C
bc
in the device
10
of FIG.
1
. Parasitic resistance R
b
can also be reduced by the low resistance P
+
polycide base connectors.
However, the device
10
′ of
FIG. 2
still has certain deficiencies. First of all, because two polysilicon (polycide) processes are used to achieve the self-aligned BJT, the entire process complexity is increased. Secondly, the P
+
base contact regions
24
and
26
are formed before a thermal cycle is used to form the N
+
emitter region
29
by out-diffusion from the N
+
polysilicon region
30
. This thermal cycle will cause the P
+
impurities in the P
+
regions
24
and
26
to out-diffuse, thereby enlarging the size of the P
+
regions
24
and
26
. This in turn can cause N
+
emitter region (region
29
) to P
+
base contact region (regions
24
and
26
) junction leakage. In addition, C
bc
will be increased due to the increase in the size of the P
+
regions
24
and
26
.
Moreover, because the P
+
base contact regions
24
and
26
are formed by out-diffusion from the P
+
links
54
and
56
, only polysilicon or polycide can be used for these links and this results in a large base interconnection resistance. Furthermore, since the emitter width (W
E
) is equal to the total diffusion area width (W
1
) minus the partial width of the two P
+
polycide base connectors (W
p1
+W
p2
) minus two times the spacer width (between the emitter
30
and P
+
polycide base connectors
54
and
56
), the emitter width cannot be easily controlled, adversely affecting BJT device characteristics.
To solve these issues a second proposed BJT
10
″ with a self-aligned base contact is formed using a process as depicted in FIG.
3
. Using conventional front end processes, the N
+
layer
14
is formed on the substrate
12
. The N-type collector region
16
is formed and then the field oxide (FOX) regions
18
are formed on the substrate surface. The deep collector connector region
20
is then formed by diffusion or ion implantation into the N-type well
16
. Thereafter, the base connector regions
54
and
56
and the emitter region
28
are formed by first depositing a polysilicon layer, patterning the polysilicon layer using photolithography and etching.
The distance W
E
is defined by the photolithographic process. The emitter region
28
includes the N
+
polysilicon (polycide) region
30
formed on the surface of the substrate and the N
+
diffusion region
29
. Spacers, such as oxide spacers
32
, are located on either side of the N
+
polysilicon region
30
. Impurities are thermally driven out of the emitter region
30
to form the N
+
diffusion region
29
and out of the base contact regions
54
and
56
to form P
+
diffusion areas
24
and
26
, respectively. Two metal contacts
36
and
38
connect to the P
+
base contact regions
24
and
26
. A third metal contact
40
connec

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