Self aligned dual inlaid patterning and etching

Details Self aligned dual inlaid patterning and etching Self aligned dual inlaid patterning and etching

2000-05-08

2001-09-11

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S618000, C438S687000, C438S700000, C438S743000

Reexamination Certificate

active

06287960

ABSTRACT:

FIELD OF THE INVENTION
The present invention is related to the field of semiconductor processing and more particularly to a process of forming a dual inlaid interconnect structure with a self aligned contact.
RELATED ART
In the field of semiconductor fabrication, dual inlaid interconnect processing is well known. In a dual inlaid interconnect process (also referred to herein as a dual inlaid process), each interconnect level and its corresponding contact level are formed by etching patterns into an underlying interlevel dielectric (ILD) layer. After the formation of the patterns in the ILD layer, a conductive material such as, for example, copper is deposited and typically thereafter polished with a chemical mechanical polish (CMP) process. Variations on dual inlaid processes include trench-first processes, via-first processes, and buried-via processes. See, for example, Singer,
Dual Damascene Challenges Dielectric Etch
; Semiconductor International, Pages 68-72 (August, 1999).
Turning now to
FIG. 1
, a partial cross sectional view of a semiconductor substrate
10
illustrating one embodiment of a conventional dual inlaid process is depicted. In
FIG. 1
, wafer
10
includes a substrate
100
on which an interconnect
102
has been formed. Interconnect
102
may comprise any of a variety of conductive materials including, as examples, aluminum, copper, or polysilicon. Following the formation of interconnect
102
, an etch stop layer (ESL)
104
is formed over substrate
100
. A first ILD layer
106
is then deposited over ESL
104
and a second ESL
108
is then deposited on first ILD layer
106
. A second ILD layer
110
is formed on second ESL
108
. A resist layer
112
is then formed and patterned over second ILD layer
110
. As depicted in
FIG. 1
, photoresist layer
112
has been patterned and a first etch step has been performed to etch a trench into second ILD layer
110
and through the second ESL
108
. Following the formation of the trench in second ILD layer
110
, the photoresist layer
112
is removed.
Turning now to
FIG. 2
, a subsequent processing step is depicted in which a second photoresist layer
202
has been deposited and patterned over second ILD layer
110
in preparation for the formation of a contact through the first ILD layer
106
to interconnect
102
. As depicted in
FIG. 2
, the patterning of the photoresist layer
202
can result in a misalignment of the contact with respect to the underlying trench and interconnect. It will be appreciated by those skilled in semiconductor fabrication, that the misalignment of photoresist layer
202
undesirably exposes portions of second ILD layer
110
.
Turning now to
FIG. 3
, a cross section view following a subsequent etch process is illustrated. As seen in
FIG. 3
, the misalignment of photoresist layer
202
resulted in a contact opening
302
that undesirably extends below an upper surface of substrate
100
at the perimeter of interconnect
102
to expose sidewall portions of interconnect
102
. In addition, if the contact opening
302
were in close proximity to an adjacent trench (not depicted in FIG.
3
), the misalignment could result in a narrowing of the ILD layer
110
between contact opening
302
and the adjacent trench. If the dimensions of an ILD layer
110
between adjacent contact
302
and an adjacent trench falls below a minimum specified value (i.e., minimum pitch), a subsequent etch or polish process could create an unintended short between contact
302
and an adjacent trench. Therefore, it would be desirable to implement a process that minimizes the susceptibility of a dual inlaid process to contact misalignment without significantly increasing the cost or complexity of the process.


REFERENCES:
patent: 6063711 (2000-05-01), Chao et al.
patent: 6083822 (2000-07-01), Lee
patent: 6100648 (2000-08-01), Jang
patent: 6174810 (2001-01-01), Islam et al.

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