Self aligned dual damascene method

Details Self aligned dual damascene method Self aligned dual damascene method

1999-10-15

2002-04-02

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S634000, C438S637000, C438S638000, C438S639000, C438S666000, C438S668000, C438S700000, C438S740000

Reexamination Certificate

active

06365504

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a dual damascene method for producing conductive lines and via plugs, and more particularly, to a self aligned dual damascene method for interconnecting metal conductive lines and via plugs in integrated circuits of semiconductor devices so as to connect metal conductive lines in multilayers.
2. Description of the Prior Art
After producing active and/or passive devices on a semiconductor substrate, metal conductive lines on the devices should be connected. The metal conductive lines are usually laid in multilayer forms. As the integration density of semiconductor devices increases, the interconnection of metal lines in different layers plays an important role and impacts on device performance.
The dual damascene method, which mainly deposits and fills metal conductive line openings and via holes between metal conductive lines with a conductive material in one step, is applied to connect metal lines of multilayers in semiconductor devices. Such a method has improved the process of the conventional interconnection between metal conductive lines. For example, in the method, processing steps have been decreased. However, the dual damascene method still needs to be improved to meet stricter process requirements and challenges.
Steps of a conventional self aligned dual damascene method are shown in
FIGS. 1
a
to
1
d.
First, as shown in
FIG. 1
a,
a first etch stop layer
4
on a second insulating layer
3
is etched by utilizing a second photoresist
10
of via pattern as an etching mask. This step is used for fabricating a via hole in the subsequent steps. Then, as shown in
FIG. 1
b,
after the second photoresist
10
is removed and a third insulating layer
5
is deposited, a first photoresist
7
is deposited on the third insulating layer
5
and a second conductive line is patterned thereon. In
FIG. 1
c,
by utilizing the first photoresist
7
and the first etch stop layer
4
as an etching mask, the third insulating layer
5
and the second insulating layer
3
are etched and a conductive line opening
8
and a via hole
11
are formed. Then as shown in
FIG. 1
d,
a conductive material is filled in the second conductive line opening and the via hole and an interconnection of a second conductive line
12
and a via plug
13
are formed. Finally, a second etch stop layer
6
is formed on the surface of the third insulating layer
5
and the second conductive line
12
.
The conventional self aligned dual damascene method has some disadvantages and is restricted in further developments when facing the requirements of smaller critical dimensions. For example, there are some difficulties in patterning the second photoresist
10
of via holes for photolithographic and etching processes. The shrunken dimensions of via holes and process windows make manufacturing processes more difficult. Furthermore, a high aspect ratio increases difficulties in etching. The overlay tolerances in patterning the first photoresist
10
and the second photoresist
7
must be strictly controlled, otherwise misalignment will be occurred, and the first etching stop layer
4
under the second conductive line opening
8
will be overetched and the second insulating layer
3
will be damaged when the third insulating layer
5
and the second insulating layer
3
are etched to form the second conductive line opening
8
and the via hole
11
. Therefore, the size and the pattern of the via hole
11
are hard to control.
U.S. Pat. Nos. 5,614,765 and 5,795,823 respectively disclose a self aligned via dual damascene structure and a method for forming the same. In the method, conductive lines are first patterned. The mask pattern of the conductive lines contains laterally enlarged area where via openings are to be formed. After the conductive line openings with laterally enlarged areas are created, the openings are filled with a conformal material whose etch selectivity is different with respect to the one of the insulating underlayer. The conformal material is etched to form sidewalls in the enlarged area. Then the exposed insulating layer under the sidewalls is etched and via openings are formed. In the latter step, the conductive line openings and vias are filled with a conductive material. Although one mask applied in the method can be omitted the enlarged areas increase difficulties in designing circuits in such tight space; partial conductive line openings are subject to damage in etching via openings; and the residual conformal material may result in bad electric performance if the conformal material is not thoroughly removed.
The present invention discloses a novel self aligned dual damascene method which can solve the above-mentioned disadvantages of the prior art.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a novel and improved self aligned dual damascene method for increasing process windows of via photolithographic process. The process is suitable for smaller line width and can produce small-sized via in a less strict process condition.
Another object of the present invention is to provide a novel and improved self aligned dual damascene method for decreasing etching aspect ratio such that small via holes can be etched completely.
A further object of the present invention is to provide a novel and improved self aligned dual damascene method for providing symmetric metal conductive lines extending on vias. The overlay tolerances caused by the misalignment between a conductive line mask and a via mask can be avoided. Product yields can be significantly increased. And the method can be applied to smaller line width processes.
A still further object of the present invention is to provide a novel and improved self aligned dual damascene method for applying to low dielectric constant material processes. A part of the low dielectric constant material which does not need to be etched can be protected from the etching damage.
To achieve the above objects and overcome disadvantages of the prior art, the present invention discloses a method for fabricating an interconnection between a conductive line and a via plug on an insulating layer. The method comprises the following steps: First, a conductive line pattern is formed on the insulating layer. Then the upper part of the insulating layer is etched and the conductive line pattern is formed on the insulating layer and a conductive line opening is formed. Then a protective layer is deposited on sidewalls of the conductive line opening and conductive line spacers on the sidewalls are formed. A via pattern is formed on the insulating layer above the conductive line spacers. The opening of the via pattern is substantially larger than the width of the conductive line opening. The substantially enlarged via pattern expands the process windows of the via photolithographic process and makes it possible to produce a smaller line width interconnection. The lower part of the insulating layer exposed between the conductive line spacers is etched by utilizing the conductive line spacers as an etching mask such that the upper part of the insulating layer is protected. Then a via hole is formed. The conductive line spacers protect the insulating layer from being etched and allow the low dielectric constant material processes to be performed. And, the conductive line opening and a via hole are filled with a conductive material. An interconnection of the conductive line and a via plug is formed. The introduction of the conductive line spacers not only provides better alignment between the conductive lines and vias but also provide better control of a small via and provides better coverage effects in depositing and filling metal between the conductive line openings and via holes.


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patent: 5719089 (1998-02-01), Cherng et al.
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patent: 6066556 (2000-05-01), Jeong
patent: 6087252 (2000-07-01), Lu
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