Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1991-08-29
1994-01-11
Crane, Sara W.
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257315, 257316, H01L 2968, H01L 2978
Patent
active
052784398
ABSTRACT:
An EEPROM cell structure includes two floating gate transistors separated by a select gate transistor with the select transistor being shared by the two floating gate transistors in programming, reading, and erasing a floating gate transistor. The floating gates of the two transistors are formed from a first polysilicon layer, the control gates of the two transistors are formed from a second polysilicon layer, and the select gate is formed from a third doped polysilicon layer. The channel length of the select gate transistor is fully self-aligned to the floating gate transistors. A word line is formed over the control gates and forms the select gate. The word line runs generally perpendicular to bit lines which contact the drain regions of the two floating gate transistors. Accordingly, a virtual ground flash EEPROM memory array can be fabricated using the EEPROM cell structure.
REFERENCES:
patent: 4417264 (1983-11-01), Angle
patent: 4513397 (1985-04-01), Ipri et al.
patent: 4868629 (1989-09-01), Eitan
patent: 4964080 (1990-10-01), Tzeng
patent: 5021848 (1991-06-01), Chiu
patent: 5099297 (1992-03-01), Hazani
K. Naruke, "A New Flash-Erase EEPROM Cell with a Sidewall Select-Gate on its Source Side," IEDM 0603-0606 1989.
Chang Kuo-Tung
Ma Yueh Y.
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