Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
2000-12-21
2002-09-17
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S379000, C438S240000, C438S253000, C438S254000, C257S267000, C257S306000, C257S758000
Reexamination Certificate
active
06451667
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to the fabrication of semiconductor devices, and more particularly to metal-insulator-metal (MIM) capacitors.
BACKGROUND OF THE INVENTION
Semiconductors are widely used for integrated circuits for electronic applications, including radios, televisions and personal computing devices, as examples. Such integrated circuits typically include multiple transistors fabricated in single crystal silicon. It is common for there to be millions of semiconductor devices on a single semiconductor product. Many integrated circuits now include multiple levels of metallization for interconnections.
The manufacturing process flow for semiconductors is generally referred to in two time periods: front-end-of-line (FEOL) and back-end-of-line (BEOL). Higher temperature processes are performed in the FEOL, during which impurity implantation, diffusion and formation of active components such as transistors occurs. Lower temperature processes take place in the BEOL, which generally starts when the first metallization layer is formed. There is a defined thermal budget during the BEOL to prevent diffusion of metal into dielectric, and avoid flowing of the metal lines, which can cause voids and result in device failures. Exposing a semiconductor wafer to high temperatures, e.g., exceeding 400 degrees C., can also cause the impurities to move about.
For many years, aluminum has been used for the conductive material comprising the interconnect layers of semiconductor devices. Usually an aluminum alloy with a small amount of copper and silicon is used. For example, a prior art aluminum conductive alloy may comprise 2% silicon to prevent the aluminum from diffusing into the surrounding silicon, and 1% copper, to control electro-migration and lead breakage due to Joule's heat.
The semiconductor industry continuously strives to decrease the size and increase the speed of the semiconductor devices located on integrated circuits. To improve the speed, the semiconductor industry is changing from aluminum to copper for metallization layers. Copper has a low resistivity compared to aluminum, resulting in faster current capability when used as a conductive material. Also, the industry is moving towards using low-dielectric constant (k) materials as insulators between conductive leads and the various metallization layers to reduce the overall size of the semiconductor devices.
Using copper as the material for metallization layers has proven problematic for various reasons. One problem with using copper for metallization layers is in the fabrication of MIM capacitors. Once a metallization layer has been applied, when copper is used, the semiconductor wafer cannot be exposed to temperatures higher than around 400° C., because copper may be damaged at temperatures higher than this.
MIM capacitors (MIMcaps) are used to store a charge in a variety of semiconductor devices, such as mixed signal and analog products. MIMcaps typically require a much lower capacitance than deep trench memory capacitors used in dynamic random access memory (DRAM) devices, for example. A MIMcap may have a capacitance requirement of 1 fF/micrometer
2
, for example.
Prior art MIMcaps are manufactured in the BEOL by forming the bottom capacitive plate in the first or subsequent horizontal metallization layer of a semiconductor wafer. A second mask, pattern and etch step is required to form the top capacitive plate. Alternatively, MIMcaps are formed between horizontal metallization layers in the BEOL in additional horizontal layers, with each plate requiring a separate pattern and etch level.
FIG. 1
shows a prior art horizontal MIMcap having a bottom plate
16
formed within an insulating layer
14
. The bottom plate is formed over a workpiece
12
which may include a substrate and other active components, not shown. A capacitor dielectric
18
is deposited over the bottom capacitor plate
16
and insulating layer
14
. A top capacitor plate
20
is formed over the capacitor dielectric
18
.
A horizontal MIMcap
10
requires a large amount of surface area of a semiconductor wafer. The MIMcap
10
shown is a large flat capacitor positioned parallel to the wafer surface covering a large area of the chip, and does not provide a high area efficiency. Furthermore, manufacturing a horizontal MIMcap
10
requires more than one metallization layer to fabricate the bottom
16
and top
20
plates.
What is needed in the art is a MIM capacitor that utilizes wafer area more efficiently than prior art MIMcaps.
SUMMARY OF THE INVENTION
These problems are generally solved or circumvented by the present invention, which achieves technical advantages as a vertical MIM capacitor formed within a single insulating layer of a semiconductor wafer.
Disclosed is a method of fabricating a MIMcap, comprising forming an insulating layer, forming at least one first conductive line within the insulating layer, and forming at least one trench abutting the first conductive line within the insulating layer. A capacitor dielectric is deposited over the insulating layer, trench, and the first conductive line, and the trench is filled with a conductive material to form a second conductive line.
Also disclosed is a MIMcap, comprising an insulating layer, at least one first conductive line formed within a top portion of the insulating layer, at least one second conductive line disposed proximate the first conductive line within the top portion of the insulating layer, and a capacitor dielectric disposed between at least the first conductive line and the second proximate conductive line.
Further disclosed is a MIM capacitor, comprising an insulating layer disposed over a substrate, a plurality of conductive metal lines formed within the insulating layer, and a capacitor dielectric disposed between the conductive metal lines, wherein two of the conductive metal lines comprise the plates of a vertical MIM capacitor.
Advantages of the invention include providing a vertical MIM capacitor that utilizes wafer area more efficiently than prior art horizontal MIMcaps. The vertical MIMcap described herein may be five times smaller, for example, than horizontal MIMcaps producing the same capacitance. Only one mask level is required, and the structure is self-aligning, relaxing optical lithography critical dimensions and overlay tolerance. The vertical MIMcap may be formed in the same inter-level dielectric as metal leads in a metallization layer. The depth of the conductive lines may be the same as the inter-level dielectric thickness to increase the capacitor area efficiency. A dielectric cap layer may serve as a CMP or etch stop for removing subsequently-deposited conductive materials. The capacitor dielectric of the vertical MIMcap also serves as a cap layer for the metal used to fill the capacitor plate. A vertical double-sided MIMcap and a comb capacitor may be produced in accordance with the present invention.
REFERENCES:
patent: 5654581 (1997-08-01), Radosevich et al.
Ruichen Liu, et al., Single Mask Metal-Insulator-Metal (MIM) Capacitor with Copper Damascene Metallization for Sub-0.18 &mgr;m Mixed Mode Signal and System-on-a-Chip (SoC) Applications; Proc. 2000 IITC pp. 111-113 (2000).
R. Mahnkopf, et al., “System on a Chip” Technology Platform for 0.18 &mgr;m Digital, Mixed Signal & eDRAM Applications; Digest 1999 IEDM pp. 849-852 (1999).
M. Armacost, et al., A High Reliability Metal Insulator Metal Capacitor for 0.18 &mgr;m Copper Technology; Digest 2000 IEDM (2000, in press).
Elms Richard
Infineon - Technologies AG
Luu Pho M.
Slater & Matsil LLP
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