Self-aligned contact structures using high selectivity etching

Details Self-aligned contact structures using high selectivity etching Self-aligned contact structures using high selectivity etching

1998-12-10

2001-01-09

Hardy, David (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

With means to control surface effects

Insulating coating

C257S900000

Reexamination Certificate

active

06172411

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to a high selectivity etching method for use in forming contact holes in self-aligned contact structures. More particularly the invention relates to selecting dielectrics, etching methods, and etchants to achieve high selectivity etching.
(2) Description of the Related Art
U.S. Pat. No. 4,954,867 to Hosaka describes the use of a layer of silicon oxy-nitride to protect the gate electrode and wirings from oxidation during high temperature processing steps. The invention does not describe the use of highly selective etching methods.
U.S. Pat. No. 5,286,667 to Lin et al. describes the use of silicon nitride or silicon oxy-nitride barrier layers in the fabrication of metal oxide semiconductor field effect transistors. The barrier layer aids endpoint detection for a plasma etch. The invention does not describe the use of highly selective etching methods.
U.S. Pat. No. 5,364,804 to Ho et al. describes a method of forming a self-aligned contact. The method uses tow silicon nitride layers but does not the use of highly selective etching methods.
U.S. Pat. No. 4,455,737 to Godejahn, Jr. describes a method of forming self-aligned gates and contacts for FET devices wherein mask alignment tolerances are increased and rendered non-critical.
SUMMARY OF THE INVENTION
The fabrication of semiconductor integrated circuits frequently requires the use of high selectivity etching for process steps such as etching contact holes during the formation of a self-aligned contact structure. Problems can be encountered in steps such as the etching of contact holes in the formation of a self-aligned contact structure, as will be described with reference to FIG.
1
.
FIG. 1
shows an electrode
14
formed on a substrate
10
having devices, not shown, and an isolation region
12
formed therein. The isolation region can be a region such as a shallow trench isolation, as shown in
FIG. 1
, or a field oxide region. A hard mask cap
18
of an oxide, such as silicon oxide, is formed on the electrode
14
and silicon oxide spacers
16
are formed on the sidewalls of the electrode
14
and the oxide cap
18
. A silicon nitride liner
22
is formed over the substrate
10
covering the hard mask cap
18
and silicon oxide spacers
16
. The spacers
16
are part of a self-aligned contact structure used for forming device regions, not shown in FIG.
1
.
An oxide layer
24
is then formed over the silicon nitride liner
22
and a layer of photoresist
26
is formed over the oxide layer
24
. The layer of photoresist
26
is patterned to form a contact hole
21
which is typically formed using dry anisotropic etching with the silicon liner
22
acting as an etch stop and providing protection for the silicon oxide spacers
16
, the oxide cap
18
, and the shallow trench isolation region
12
or field isolation region. Frequently the edge
34
of the silicon nitride liner
22
at the point where the liner
22
passes over the junction between the oxide cap
18
and one of the silicon oxide spacers
16
is very thin allowing the etching to punch through the liner during the etching of the contact hole
21
. The punch through of the silicon nitride liner allows the contact hole etching to attack the oxide cap
18
and the silicon oxide spacers
16
.
One method of protecting against attack of the spacers
16
and hard mask cap
18
during the contact hole etching is to form the spacers
16
and hard mask cap
18
from silicon nitride. The silicon nitride liner
22
then covers a silicon nitride cap
18
and silicon nitride spacers
16
. This protects the silicon nitride cap
18
and silicon nitride spacers
16
from attack due to the problems of punch through of the silicon nitride liner
22
during the contact hole
21
etching but leads to the problem of attack of the silicon nitride cap
18
and the silicon nitride spacers
16
during the removal of the silicon nitride liner
22
when the contact hole
21
is completed.
It is a principle objective of this invention to provide a method of contact hole etching having sufficient etching selectivity to protect the dielectric cap on the electrode and the dielectric spacers on the sidewalls of the electrode in a self-aligned contact structure.
It is another principle objective of this invention to provide a self-aligned contact structure comprising an electrode, a dielectric cap on the electrode, and dielectric spacers on the sidewalls of the electrode which will not be attacked during contact hole etching.
These objectives are accomplished by forming the dielectric cap on the electrode and the dielectric spacers on the sidewalls of the electrode from silicon oxy-nitride. A layer of silicon nitride is then formed over the substrate covering the silicon oxy-nitride cap and silicon oxy-nitride spacers with silicon nitride liner. The contact hole is then etched using an etching means and etchant which has a much greater etch rate for oxide than for silicon nitride or for silicon oxy-nitride. The silicon nitride liner is then removed using an etching means and etchant which has a much greater etch rate for silicon nitride than for silicon oxy-nitride.


REFERENCES:
patent: 4455737 (1984-06-01), Godejahn, Jr.
patent: 4954867 (1990-09-01), Hosaka
patent: 5286667 (1994-02-01), Lin et al.
patent: 5364804 (1994-11-01), Ho et al.
patent: 5488246 (1996-01-01), Hayashide et al.
patent: 5696036 (1997-12-01), Su et al.
patent: 5780338 (1998-07-01), Jeng et al.
patent: 5869403 (1999-02-01), Becker et al.
patent: 5930627 (1999-09-01), Zhou et al.
patent: 5948701 (1999-09-01), Chooi et al.
patent: 6027971 (2000-02-01), Cho et al.
patent: 6060766 (2000-05-01), Mehta et al.
patent: 0 259 826 (1988-03-01), None

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