Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1998-04-01
2001-01-30
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S710000, C438S712000, C438S714000
Reexamination Certificate
active
06180530
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to processes used to fabricate semiconductor devices, and more specifically to a process used to create an extended, self-aligned contact region, for a static random access memory, (SRAM), device.
(2) Description of Prior Art
Static random access memory, (SRAM), cells are usually designed to include six, metal oxide semiconductor field effect transistors, (MOSFET), usually four N channel, and two P channel, MOSFETs. The SRAM performance and cost objectives have been successfully addressed by the ability of the semiconductor industry to fabricate SRAM devices, using sub-micron features. The smaller features result in a decrease in performance degrading capacitances and resistances, while also allowing a greater number of smaller SRAM chips, to be obtained from a specific size starting substrate, thus reducing the manufacturing cost of a specific SRAM chip. In addition the processes and structures, needed to create metal contacts to source and drain regions, have been optimized via use of a self-aligned contact, (SAC), structure, contacting underlying source and drain regions located in the semiconductor substrate, between gate structures. The use of SAC structures, have also resulted in additional miniaturization of SRAM devices, allowing performance and cost objectives to be further enhanced.
The use of SAC structures, for contact to source and drain regions of SRAM devices, has however made it difficult to reduce the pitch between the source and drain regions, and the adjacent gate structures. The shrinking space between gate structures, has resulted in the creation of narrow SAC structures, thus resulting in SAC structures with higher resistance than counterparts fabricated using wider SAC structures. This invention will describe a new SAC design in which the SAC opening is comprised of a narrow opening, between gate structures, allowing the desirable SRAM miniaturization to be achieved, but also comprised with a wider opening component, extended to overlay a non-active SRAM region. Thus a tungsten fill of the two shaped SAC opening creates a SAC structure that offers: a low resistance local interconnect level; a narrow spacing between gate structures; and a wide landing area for an overlying metal contact structure.
Prior art, such as Kiyono, et al, in U.S. Pat. No. 5,460,995, show a contact structure, for an SRAM device, however the SAC design and process, used for this invention, were not similar to this invention.
SUMMARY OF THE INVENTION
It is an object of this invention to create a SAC structure for a SRAM cell.
It is another object of this invention to use a SAC opening, comprised of a narrow portion, exposing source and drain regions, in the narrow spaces between gate structures, and comprised of a wider portion, overlying non-active regions of the SRAM device.
It is still another object of this invention to fill the SAC opening with tungsten, creating a SAC structure that contacts source and drain regions, in the narrow spaces between gate structure, and allows contact to an overlying metal, in the wider portions of the SAC structure.
In accordance with the present invention a method for creating a SAC structure, used as a local interconnect layer, and used for contact to underlying source and drain regions, located in the narrow spaces between gate structures, and for contact to an overlying metal structure, has been developed. A two shaped, SAC opening, is formed in a first insulator layer, comprised of a narrow SAC opening shape, exposing source and drain regions, between gate structures, and comprised of a wider SAC opening, connected to the narrow SAC opening, overlying a non-active region of a SRAM device. A first tungsten plug is formed in the two shaped, SAC opening, resulting in a SAC structure, comprised of a narrow shape, contacting source and drain regions, in the narrow spaces between gate structures, and a wider shape, overlying a non-active region of the SRAM device. After deposition of a second insulator layer, a contact hole is opened in the second insulator layer, exposing the top surface of the wider shape of the SAC structure. A second tungsten plug is formed in the contact hole, followed by the creation of an metal interconnect structure, overlying, and contacting the second tungsten plug.
REFERENCES:
patent: 5460995 (1995-10-01), Kiyono et al.
patent: 5484741 (1996-01-01), Bergemont
patent: 5677557 (1997-10-01), Wuu et al.
patent: 5795827 (1998-08-01), Liaw et al.
patent: 5814886 (1998-09-01), Mano
patent: 5817562 (1998-10-01), Chang et al.
patent: 5874359 (1999-04-01), Liaw et al.
patent: 5904521 (1999-05-01), Jeng et al.
Lee Jin-Yuan
Liaw Jhon-Jhy
Ackerman Stephen B.
Saile George O.
Taiwan Semiconductor Manufacturing Company
Utech Benjamin L.
Vinh Lan
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