Self-aligned contact process using silicon spacers

Details Self-aligned contact process using silicon spacers Self-aligned contact process using silicon spacers

1998-05-12

2000-07-25

Niebling, John F.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

438597, 438947, H01L 213205

Patent

active

060936274

ABSTRACT:
A method of forming self-aligned contact by using silicon spacers is provided. The process comprising: forming gate structures on a semiconductor substrate, the gate structure comprising a layer of gate oxide, at least one layer of conducting material and a layer of etching stop material; forming an overall conformal layer of first dielectric material, then etching back the first dielectric layer to form first side wall spacers on both sides of the gate structure; forming an overall conformal layer of etching selectivity material, then etching back the etching selectivity layer by second etching to form second side wall spacers overlying the first side wall spacers, the second side wall spacers providing an effective protecting layer over the gate structure in the successive etching process; forming and planarizing a second dielectric layer overall; forming an opening in the second dielectric layer by etching through the second side wall spacers down to said semiconductor substrate to form a self-aligned contact via, the contact via is self-aligned in the region between the second side wall spacers of two adjacent gate structures by the advantage of high etching selectivity between the second side wall spacers and the second dielectric layer; thermal oxidizing exposed second side wall spacers to form a thin first oxide layer, the first oxide layer providing an electrical isolating layer between the conducting material in contact via and the second side wall spacers.

REFERENCES:
patent: 5338952 (1994-08-01), Yamauchi
patent: 5547885 (1996-08-01), Ogoh
patent: 5834360 (1998-10-01), Tesauro et al.

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