Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Patent
1997-12-31
2000-09-26
Nguyen, Tuan H.
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
438780, 438303, H01L 214763
Patent
active
061241911
ABSTRACT:
Method and apparatus for fabricating contacts to substrate regions through a low k, low density dielectric. A cap is formed over gates and side spacers are formed along the edges of the gates so as to surround the gates in a relatively dense (e.g., silicon dioxide) insulative material. A low k or low density layer of a polymer or silica aerogel or xerogel material is formed in contact with the substrate covering the gate structures including the spacers. An unlanded contact opening is etched through the low k, low density dielectric with an etchant that provides high selectivity between the insulation surrounding the gate and the low k, low density layer.
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"Porous Xerogel Films as Ultra-Low Permittivity Dielectrics for ULSI Interconnect Applications", by Jin, List, Lee, Lee, Luttmer and Havermann, Conference Proceedings ULSI XII.COPYRGT. 1997, Materials Research Society pp. 463-469.
Chen Jack
Intel Corporation
Nguyen Tuan H.
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