Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-12-17
2004-04-20
Potter, Roy (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S346000, C257S387000, C438S229000, C438S230000, C438S233000
Reexamination Certificate
active
06724054
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to integrated circuits, and more particularly to an integrated circuit having an improved self-aligned contact structure and a method of-fabricating same.
DESCRIPTION OF THE RELATED ART
Integrated circuits (ICs) or chips require contacts or contact regions that are fabricated from an electrically-conductive material, such as, for example, a metal or alloy. The contacts enable current to flow between one part of the circuit, such as a drain or source region, and another part of the circuit and/or the outside world. A contact desirably has a relatively low electrical resistance.
The consumer desire for miniature, portable and,integrated electronic devices has forced designers to continually seek to increase the density and reduce the size of ICs, and to integrate multiple functions into a single IC. Accordingly, designers seek to reduce the size of or shrink the individual features within an IC, including the contact regions. However, as the size (i.e., the area) of a contact region decreases its resistivity undesirably increases.
In order to form contacts in such dense ICs, a process that uses the topography of the IC itself, rather than masking or photoresist processes, is used. Such a process is referred to as a self-aligned contact formation process. In the self-aligned contact formation process, spacers formed of an insulative material, such as, for example, silicon nitride, are deposited on the sidewalls of a gate electrode stack or wordlines. The spacers insulate the gate electrode from the conductive layer that is subsequently deposited to form the contact. The thickness of these spacers is a critical characteristic. A spacer having a less than desired thickness may not adequately insulate the gate from the contact, whereas a spacer having a greater than desired thickness reduces the available area for the contact, thereby undesirably increasing the resistance of the contact.
Typically, the thickness of a spacer is greatest proximate the surface of the silicon wafer, and is smallest at the upper comers of the gate electrode structure (i.e., furthest from the surface of the silicon wafer). The thickness of the spacers at the upper comers of the gate electrode structure must be maintained at a minimum in order to prevent the gate electrode from shorting to the contact. However, maintaining the thickness of the spacers at the upper comers of the gate electrode results in a spacer that is thicker than necessary proximate to the surface of the silicon wafer. The increased thickness proximate the silicon surface consumes area that could otherwise be occupied by the contact, and thereby decreases the area available for the contact. Thus, the resistance of the contact is undesirably increased.
Therefore, what is needed in the art is an integrated circuit with spacers having a desired thickness proximate the upper comer of the gate electrode and having a reduced thickness proximate the silicon surface, and a method of fabricating same.
Furthermore what is needed in the art is an integrated circuit with increased contact area (and thus reduced contact resistance) and yet with sufficient insulation at the upper comers of the gate electrode, and a method of fabricating same.
SUMMARY OF THE INVENTION
The present invention provides a method for fabricating a self-aligned contact having reduced contact resistance in an integrated circuit.
The invention comprises, in one form thereof, a method that includes defining first spacer layers over the sidewalls of a pair of wordline stacks. An oxide layer is deposited over the tops of the wordline stacks, the first spacer layers and a surface of the substrate disposed between the first spacer layers. The oxide layer is removed from the first spacer layers, thereby forming a remaining oxide layer that covers the surface of the substrate disposed between the first spacer layers. Second spacer layers are formed over the first spacer layers, and cover respective portions of the remaining oxide layer. The remaining oxide layer is removed to thereby form undercut regions. The undercut regions are substantially filled with contact material during formation of the contact.
An advantage of the present invention is that the contact area is increased, and the resistance of the contact is reduced, relative to conventional contacts.
REFERENCES:
patent: 5953614 (1999-09-01), Liu et al.
patent: 5998290 (1999-12-01), Wu et al.
patent: 6159835 (2000-12-01), Visokay et al.
patent: 6198144 (2001-03-01), Pan et al.
patent: 6235621 (2001-05-01), Jeng et al.
patent: 6281539 (2001-08-01), Mandelman et al.
patent: 6284593 (2001-09-01), Mandelman et al.
patent: 6465294 (2002-10-01), Tsai et al.
Kang Woo-tag
Malik Rajeev
Seitz Mihel
FitzGerald Esq. Thomas R.
Infineon - Technologies AG
Potter Roy
LandOfFree
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