Self-aligned contact formation

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

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257755, 257756, H01L 2904

Patent

active

054913551

ABSTRACT:
A polycrystalline silicon layer is deposited and patterned to define a level of interconnect. Contact opening to lower conductive layers are then defined and patterned. A refractory metal such as tungsten is selectively deposited over the device, so that it adheres to the polycrystalline silicon in the interconnect leads and silicon of the lower conductive layer which is exposed in the contact openings. This provides a low resistance interconnect, and good, metal, contacts to underlying layers. Shared contacts between two or more polycrystalline silicon interconnect layers and in underlying conductive layers such as a substrate are easily formed using this technique.

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patent: 4851362 (1989-07-01), Suzuki et al.
patent: 4878105 (1989-10-01), Hirakawa et al.
patent: 5250846 (1993-10-01), Kondo

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