Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2003-05-09
2004-09-14
Clark, Jasmine (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S774000, C257S760000, C257S797000
Reexamination Certificate
active
06791190
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor fabrication and, more particularly, to a self-aligned contact/borderless contact opening and a method for forming a self-aligned contact/borderless contact opening.
2. Description of the Related Art
In self-aligned contact (SAC) processes, it becomes more difficult to produce accurate results as the aspect ratio increases. The aspect ratio is the ratio of the depth of the layer (or layers) being etched as compared to the width of the feature (e.g., contact hole) being formed by the etching process. Therefore, as device densities increase with reduced feature width, the aspect ratio also increases.
Further, many conventional SAC processes use protective layers. The protective layers are typically applied in thicker layers. These thicker layers further increase the aspect ratio of the SAC process. By way of example, a conventional SAC process includes a silicon nitride cap layer and a silicon nitride spacer for protecting the gate structure during the contact opening etching process. The silicon nitride cap layer (cap layer) is typically greater than 1000 angstroms in thickness. The thicker protective layer is required to provide the desired selectivity control and protection of the gate structures during the etching processes used to form the SAC opening.
Higher aspect ratios in conventional SAC processes can also reduce the effective lithography window, which further complicates the SAC process.
In view of the foregoing, there is a need for a method for reducing the aspect ratio of the SAC process and thereby increase the lithography window.
SUMMARY OF THE INVENTION
Broadly speaking, the present invention fills this need by providing SAC processes having reduced aspect ratios. In one embodiment, the reduced aspect ratios are achieved by using a thinner protective layer or layers to protect the gate structure during an etching process. Several inventive embodiments of the present invention are described below.
In accordance with one aspect of the present invention, a method for forming a self-aligned contact (SAC)/borderless contact opening is provided. In this method, a shallow trench isolation (STI) structure is formed in a substrate to define an active area. A gate structure, which includes a cap layer, is formed. The gate structure is formed on the substrate and oriented perpendicular to the STI structure and the active area. An oxide spacer is formed on at least one of the sidewalls of the gate structure. A conformal liner layer is formed on the substrate covering the gate structure, the oxide spacer, and the STI structure. An inter-layer dielectric (ILD) layer is formed on the substrate covering the liner layer. The ILD layer is patterned to define a SAC/borderless contact opening. In one embodiment, the ILD layer is etched to form the SAC/borderless contact opening.
In one embodiment, the oxide spacer and the cap layer are comprised of silicon oxide and the conformal liner layer is comprised of silicon nitride or silicon oxynitride. In one embodiment, the ILD layer is etched with a C
4
F
6
/O
2
/Ar mixture or a C
5
F
8
/CH
2
F
2
mixture.
In one embodiment, the liner layer includes several liner layers. In one embodiment, the liner layers include a first liner layer that includes at least one of the group consisting of a silicon nitride layer and a silicon oxynitride layer. The liner layers can also include a second liner layer disposed between the first layer and the cap layer, with the second liner layer being comprised of silicon oxide.
In accordance with another aspect of the present invention, a SAC/borderless contact structure is provided. This structure includes a substrate and a shallow trench isolation (STI) structure formed in the substrate to define an active area. A gate structure having a cap layer thereon is formed on the substrate and oriented perpendicular to the STI structure and the active area. The structure further includes an oxide spacer on a sidewall of the gate structure. A conformal liner layer is formed on the substrate and covers the gate structure, the oxide spacer, and the STI structure. An inter-layer dielectric (ILD) layer is formed on the substrate and covers the liner layer. The ILD layer is patterned to define a SAC/borderless contact opening.
Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.
REFERENCES:
patent: 6204185 (2001-03-01), Hsu
patent: 6429487 (2002-08-01), Kunikiyo
patent: 6436765 (2002-08-01), Liou et al.
patent: 2335539 (1999-09-01), None
Clark Jasmine
Macronix International Co. Ltd.
Martine & Penilla LLP
LandOfFree
Self-aligned contact/borderless contact opening and method... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Self-aligned contact/borderless contact opening and method..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Self-aligned contact/borderless contact opening and method... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3247823