Self-aligned connection to underlayer metal lines through unland

Details Self-aligned connection to underlayer metal lines through unland Self-aligned connection to underlayer metal lines through unland

1998-04-06

2000-01-18

Niebling, John F.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438624, 438639, 438666, 438668, 438675, H01L 214763

Patent

active

060157518

ABSTRACT:
Methods for forming via holes in inter-level dielectric layers for via connections to underlying electrodes are described. The underlying electrodes do not have electrode pads or enlarged areas of the electrode to contact the conductive material in the via hole. The method avoids the problems of oversize vias and mis-aligned vias. One of the embodiments uses extra wide dielectric spacers formed in two steps on the sidewalls of the underlying electrodes. The spacers provide an effective electrode width greater than the actual width of the electrode thereby increasing the tolerance for both the size and the alignment of the via holes. Another embodiment uses alternate layers of two dielectric materials and etching methods which etch each of the two materials selectively. The dielectric material which is not etched in each step serves as an etch stop layer.

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