Self-aligned composite insulator with sub-half-micron multilevel

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

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Details

438618, 438622, 438629, 438631, 438633, 438634, 438637, 438674, 438675, 257750, 257752, 257760, 257762, 257763, 257764, 257765, 257766, H01L 2144, H01L 214763, H01L 23485, H01L 2352

Patent

active

061331392

ABSTRACT:
The present invention relates generally to a new sequence of methods and materials to improve the process yield and to enhance the reliability of multilevel interconnection with sub-half-micron geometry by making judicious use of composite insulators to prevent metal thinning over hard metal via plugs and by preventing process induced metal spike formation. The method takes advantage of the double damascene process. The metal spikes and the metal thinning resulting from over etch process is prevented in this method by using a pair of insulators which require different chemistries for etching.

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