Self-aligned clock recovery circuit with proportional phase...

Details Self-aligned clock recovery circuit with proportional phase... Self-aligned clock recovery circuit with proportional phase...

1998-07-20

2002-02-12

Ghayour, Mohammad H. (Department: 2734)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S371000, C375S373000, C331S011000, C331S012000, C713S400000, C713S500000

Reexamination Certificate

active

06347128

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates generally to clock recovery circuitry and digital data regeneration.
Clock recovery circuits are employed within optical and RF receivers to establish synchronization between a locally generated clock and the timing of a bit stream within a received data signal. The local clock, once synchronized to the incoming data signal, is used to control regeneration of the data.
FIG. 1
is a simplified block diagram of a conventional clock recovery and data regeneration circuit
10
. A non-return-to-zero (NRZ) data signal is received by an optical or RF receiver. A phase lock loop comprised of a phase detector
12
, loop filter
14
and voltage controlled oscillator (VCO)
16
derives a recovered clock signal synchronized to the symbol stream of the data signal. Phase detector
12
continually compares the VCO clock phase to the data signal phase and provides an output signal to the loop filter accordingly. High data rate systems often employ a sampling type of phase detector in which samples of the data signal are taken at the data transition (crossover) regions as well as at the approximate midpoints of each data bit to achieve precise alignment of the clock. Loop filter
14
low pass filters the phase detector output to provide a control voltage to VCO
16
to adjust the clock frequency (align the clock) so that it tracks the data rate of the data signal. Regeneration of the data signal is accomplished by means of a comparator
17
that compares the data signal level to a decision threshold level V
DT
to generate a solid logic level, which is then routed through a D flip-flop
18
clocked by the synchronized VCO clock.
As data rates in fiber optic and microwave systems continue to increase, alignment of jittered data and the recovered clock inside the receiver becomes ever more critical. Misalignment results in a reduced sensitivity to jitter and, consequently, reduces the allowable bandwidth of the optical signal (reduced fiber span).
Regenerator architectures employing sampling phase detectors are promising, since alignment is an inherent property for these types of circuits. Also, the sampling phase detector output is generated through post-processing of data samples; in demultiplexing regenerators, such processing can be deferred to lower bit rates.
A drawback to the sampling phase detector, however, is that the phase detector characteristic is a signum function (output which is either zero, a predetermined positive value or negative value) which renders the jitter properties of the receiver non-linear. Analog linear phase detectors, by contrast, provide an output which is proportional in amplitude to the phase error between the input signals, resulting in good jitter tolerance properties. Applications that require jitter transfer compliance, such as SONET regenerators or optical translators, have therefore been dominated by clock recovery circuits with linear, but non-self-aligned, phase detectors.
SUMMARY OF THE DISCLOSURE
The present disclosure pertains to a self-aligned clock recovery circuit for synchronizing a local clock with an input data signal. In an illustrative embodiment, the clock recovery circuit includes a sampling type phase detector for generating an output signal based on the phase difference between the local clock and the data signal timing. The phase detector includes sampling circuitry for obtaining samples of consecutive data symbols at sampling times corresponding to transitions of the local clock, and for obtaining a data crossover sample at a sampling instant in between those of the consecutive data symbol samples. A phase shifter is employed to phase shift the local clock by an amount corresponding to a time varying modulation signal so as to obtain each data crossover sample at a variable sampling instant relative to the associated consecutive symbol samples. Logic circuitry determines whether the local clock appears to be early or late based on a comparison of the logic levels of the symbol samples and the associated data crossover sample, and provides a corresponding output signal through a filter to the local clock to adjust the clock accordingly.


REFERENCES:
patent: 4871975 (1989-10-01), Nawata et al.
patent: 5432480 (1995-07-01), Popescu
patent: 5939916 (1999-08-01), Jamal et al.
J.D.H. Alexander, “Clock Recovery from Random Binary Signals”, Electron. Lett., vol. 21, pp. 541-542, Oct. 1975.
A. Buchwald et al., “Integrated Fiber Optic Receivers”, pp. 291-304, Kluwer, 1995.

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