Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
2000-06-06
2001-12-11
Bowers, Charles (Department: 2823)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C438S298000, C438S296000, C438S174000, C438S232000, C438S270000, C438S301000, C257S336000, C257S344000, C257S396000
Reexamination Certificate
active
06329271
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to semiconductor devices, and more particularly, to a process for the manufacture of field effect transistors that exhibit a desirable reduction in the short channel effect.
BACKGROUND OF THE INVENTION
It is known that as the dimensions of field effect transistors are scaled down for faster switching speed and lower current requirements, there arises the short channel effect. In order to increase the speed, the length of the channel between the source and drain of a field effect transistor is shortened. As is channel is shortened, there is a tendency in operation for breakdown to occur between the source and drain at voltages less than would otherwise be expected. This short channel effect is generally blamed on the spread, during operation, of depletion regions of the source and drain into the channel. As the depletion regions meet or as one extends from the drain/source to the source/drain, breakdown occurs.
Various techniques have been tried to attenuate this effect. One technique, described as the halo junction technique, involves forming highly doped regions of the same conductivity type as the semiconductor body, but of higher conductivity, around portions of the drain and source excluding portions of the drain and source near the surface of the semiconductor body where the channel is formed when the transistor is biased on. This results in large steep p-n junctions that undesirably increases junction capacitance and leakage current.
Another technique uses a first blanket implantation of the semiconductor body area where a transistor is to be formed to form a buried region of the same conductivity type as the semiconductor body but of higher impurity concentration. This forms what is known as a retrograde type well. A second blanket implantation of the same conductivity type impurities is then done to modify the conductivity at and close to the surface of the semiconductor body so as to control threshold voltage. A gate dielectric layer is then formed followed by the formation of a gate. The gate is then used as a mask and there is an implantation of the source and drain, which are formed aligned to the gate. The resulting structure undesirably increases junction capacitance and leakage current.
Another known attempt to solve the short channel problem involves first implanting the surface of the chip where the inversion channel is to be formed to increase the doping at the surface, a step often practiced to control the threshold voltage of the device. This is followed by implanting the top surface more deeply to form a continuous layer extending the length of the active area that is of the same conductivity type as that of the source and drain and underlies the source and drain to limit the spread of the depletion regions.
However in such a device there is also increased undesirably the junction capacitance and the leakage current.
The present invention seeks to improve on both these techniques.
SUMMARY OF THE INVENTION
The present invention solves the problem of introducing a highly doped buried layer of the conductivity type opposite that of the source and drain that extends below the channel only along the width of the channel by forming such buried layer in a way to be self aligned with the gate and the channel. In particular, in an illustrative example, the novel process of the invention comprises the following steps. First, as is usual, there are formed over a top surface of a semiconductor body an underlying PAD silicon dioxide and an overlying PAD silicon nitride layer.
At this point, it is usual to implant the semiconductor body with acceptor ions to form a P-well where N-MOSFETs are to be formed and with donor ions to form an N-well where P-MOSFETs are to be filed. Further mention of such steps will be omitted as unnecessary. These layers are then patterned to expose the surface of regions of the semiconductor body where silicon oxide shallow trenches, characteristic of shallow trench isolation (STI) are formed and then filled with a suitable dielectric, preferably silicon oxide. Advantageously, the deposited silicon oxide layer is made to have the same height above the surface as the PAD nitride layer. This can be readily achieved by overfilling the shallow trenches, and then planarizing the surface by chemical mechanical polishing (CMP) using the PAD nitride as the etch stop.
Next, where the gate region is to be formed there is removed the PAD nitride layer that is still overlying the active area, forming a recess, but leaving the PAD oxide layer. This PAD oxide is left to protect the chip surface during the subsequent implantation of the surface. Alternatively, this PAD oxide can be etched completely away and replaced by a new thermally grown oxide layer, generally described as a sacrificial oxide layer, for use to protect the surface of the gate region during ion implantation. Now there is formed by ion implantation and aligned with the recess that defines the future gate region a buried heavily doped layer that is of the same conductivity type as that of the semiconductor body and opposite that of the future drain and source areas to be formed in the body.
The bulk region between the source and drain that includes the layer that is to be inverted to form the channel is typically described as the base region and is of the conductivity type opposite that of the source and drain regions. The process of forming a MOSFET typically includes a shallow ion implantation of the base region to set the threshold voltage V
T
of the transistor. The type of ion implanted to set the threshold voltage generally will depend on the doping modification needed to provide the desired threshold voltage. After the implantations are completed, the PAD oxide left in the intermediate region can be stripped, still leaving the PAD dual layers on either side of the implanted region.
Now there is formed a suitable gate oxide over the exposed recessed region between these PAD layers, after which polysilicon suitable for serving as the gate electrode, is deposited to overfill the recess region between the PAD layers. This gate electrode will be well aligned with the heavily doped buried layer formed by the earlier implantation. This initial gate electrode typically is covered over with another conductive layer such as tungsten silicide to form a gate stack. This gate stack is then planarized to the level of the PAD nitride layer and the STI layer. Now there is stripped the remaining PAD nitride and the underlying PAD oxide layer, after which dielectric spacers typically of silicon oxide are formed on the side walls of the gate stack. Now with the STI polysilicon layer and the gate stack as a mask, there are formed the source and drain regions by ion implantation. These will be self aligned with the deeper implanted layer that underlies each gate stack, whereby there is reached the ideal structure sought.
In an alternative embodiment, after there have been defined the active areas and these have been surrounded by the silicon oxide that provides the STI as in the first embodiment, the surface of the semiconductor body is covered with a layer of a masking material and this is patterned to expose the surface region where there is to be formed an extended gate conductor that will overlie the surface and interconnect the gates of all the transistors in a common row or column. Then the regions, including both active area regions and STI regions exposed where this pattern passes over then are etched in two steps, first in an oxide-nitride selective etch to form a pattern in the STI and the future gate regions, and then in an nitride selective etch to stop at the oxide layer over the gate region. Then there follow the implantations to form the buried layer under the gate region and to set the threshold voltage. Next there follows deposition of a gate conductor layer over the surface for filling the various gate regions and the pattern formed in the surrounding STI by the two-step etch mentioned above, as will be described more fully below.
Each of t
Akatsu Hiroyuki
Beintner Jochen
Li Yu-jun
Bowers Charles
Braden Stanton C.
Infineon - Technologies AG
Lee Hsien-Ming
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