Self aligned buried plate

Details Self aligned buried plate Self aligned buried plate

1998-03-09

2004-03-02

Norton, Nadine G. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S703000, C438S706000, C438S745000

Reexamination Certificate

active

06699794

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates generally to the manufacture of integrated circuits (ICs). More specifically, the invention relates to a method of manufacturing self aligned buried plates within a deep trench formed into a silicon substrate.
Buried plate structures formed within deep trenches that are etched into a silicon substrate are commonly used in the integrated circuit industry. These buried plate structures may be used to, for example, form integrated circuit components such as trench capacitors that may be used as memory storage nodes in devices such as DRAMs. However, the conventional vertical patterning processes used to produce these buried plates are relatively complex and, as described in more detail below, are not self-aligning. In order to more clearly illustrate these problems, a prior art process for producing a trench capacitor on a silicon wafer will be described with reference to
FIGS. 1-19
.
As indicated in
FIG. 1
, a silicon wafer
100
is provided having a deep trench
102
etched into wafer
100
. Wafer
100
typically has a thin pad oxide layer
104
and a pad nitride layer
106
formed on a top surface
108
of a silicon substrate
110
. As is known in the art, pad oxide layer
104
acts as a stress relieving layer for preventing pad nitride layer
106
from separating from silicon substrate
110
during subsequent high temperature process steps. Pad nitride layer
106
, which is typically about 200 angstroms thick, acts as a protective layer for top surface
108
of substrate
110
during subsequent process steps such as oxidation steps.
Although not illustrated in the figures, trench
102
is formed into wafer
100
using a deep trench etching process. To accomplish this, a Borosilicate glass (BSG) hard mask layer
112
is applied over pad nitride layer
106
. BSG hard mask
112
is then patterned with a resist material (not shown) and etched using a conventional hard mask etching process such as a dry etch process using an CF
4
/CF
3
/Argon etchant. One or more etching process opens BSG hard mask layer
112
(as well as pad nitride layer
106
and pad oxide layer
104
) in the areas above where deep trench
102
is to be etched. The resist material (not shown) used to pattern hard mask
112
is then removed using well known resist removing processes. Deep trench
102
is then etched using an appropriate etching process such as a dry etch using an HBr/NH
3
/O
2
etchant. In this case, the deep trench is etched to a level of about 8 microns below top surface
108
of silicon substrate
110
forming trench sidewalls
114
and
116
.
As illustrated in
FIG. 2
, once trench
102
is etched into wafer
100
, BSG hard mask layer
112
is removed using any conventional hard mask removal process such as, for example, a vapor phase etching process using HF vapor. At this point, the process steps used to form a buried plate structure within the deep trench begins.
Referring to
FIG. 3
, the first step in actually forming a conventional buried plate structure involves depositing an arsenic doped silicon tetraethylorthosilicate glass (ASG TEOS) layer
118
over pad nitride layer
106
and over the surfaces of trench
102
. As described in more detail hereinafter, ASG TEOS layer
118
is used to provide the arsenic doping for certain regions of silicon substrate
100
during subsequent annealing steps. This layer may be applied using a conventional chemical vapor deposition (CVD) technique and is typically applied at a thickness of, for example, about 40-60 nm.
Once ASG TEOS layer
118
has been applied, it is etched from the top surface of the pad nitride layer and from certain uppermost portions of trench sidewalls
114
and
116
of trench
102
. This etching process is accomplished using the process steps illustrated in
FIGS. 4-7
.
As illustrated in
FIG. 4
, a resist material
120
is first applied to wafer
100
. This resist material fills trench
102
and coats the top surface of wafer
100
with a layer of resist material. Next, as shown in
FIG. 5
, resist material
120
is recessed or etched back to a desired level within trench
102
, in this case, to a level in the range of about 5.5 to 6.5 microns above the bottom of trench
102
. This etching back of the resist exposes portions of the ASG TEOS layer at the uppermost portions of the sidewalls
114
and
116
of trench
102
. This step is accomplished using a conventional photoresist etching process. As described in more detail hereinafter, this is the step that determines the level of the first vertical patterning step for this process.
Once resist material
120
has been etched back to the desired level, ASG TEOS layer
118
is etched away from the top of wafer
100
and from the exposed portions of sidewalls
114
and
116
. A wet etching process using, for example, a BHF etchant is typically used to etch, and slightly over etch, the ASG TEOS layer. After this etching step, ASG TEOS layer
118
may be slightly recessed below the level of the remaining resist as shown in FIG.
6
. And finally, this etching process is finished by removing the remaining portions of resist material
120
using a conventional photoresist removal process. Once the resist is removed, only portions of ASG TEOS layer
118
remain with these portions covering the bottom portions of trench
102
.
Once the etching process for the ASG TEOS layer is complete, the ASG TEOS layer is annealed as illustrated in
FIGS. 8-10
. This annealing process produces an arsenic doped region within silicon substrate
110
surrounding the bottom portions of trench
102
. This arsenic doped region forms the buried plate structure. In the specific case of a trench capacitor that is being described, this arsenic doped region forms one of the plates of the capacitor.
Prior to the actual annealing step, a cap TEOS layer
122
is deposited over wafer
100
coating trench
102
as illustrated in FIG.
8
. Cap TEOS layer
122
is an undoped TEOS or ozone TEOS layer that prevents the arsenic doped TEOS
118
from doping the upper portions of trench sidewalls
114
and
116
and/or to prevent the arsenic dopant from escaping from the trench during the dopant drive anneal step. Cap TEOS layer
122
is applied using a conventional CVD technique and is typically applied at a thickness of, for example, about 400 Angstroms.
After cap TEOS layer
122
is applied, wafer
100
is annealed. During the annealing step, the temperature is elevated for an specific length of time. In this specific case, the temperature is raised to about 1050 degrees F. for a period of about 30 minutes. This high temperature moves the arsenic from ASG TEOS layer
118
into the surrounding region of silicon substrate
110
thereby forming a buried plate structure
124
within a region of silicon substrate
110
surrounding the bottom portion of trench
102
. This process is illustrated in FIG.
9
. After the annealing step, the remaining portions of ASG TEOS layer
118
and cap TEOS layer
122
are removed. This is accomplished using a conventional process such as, for example a wet etching process using, for example, a BHF etchant.
Once buried plate structure
124
is formed as described above, a nitride layer is formed on the trench walls adjacent to buried plate structure
124
using the process steps illustrated in
FIGS. 11-15
. This nitride layer acts as a dielectric for the trench capacitor. This process of forming the capacitor dielectric is the second vertical patterning step of the overall process of forming the trench capacitor. As will be described in more detail hereinafter, this second vertical patterning step must be strictly controlled so that the top of the nitride layer is at the proper level relative to buried plate structure
124
. Because two separate vertical patterning steps are used to locate the top of the nitride layer relative to the top of buried plate structure
124
, these layers are not self-aligned.
Referring now to
FIG. 11
, the process of forming the capacitor dielectric will be described. As shown in
FIG. 11
, a nitrid

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