Self-aligned bipolar transistor with very thin dielectric layer

Details Self-aligned bipolar transistor with very thin dielectric layer Self-aligned bipolar transistor with very thin dielectric layer

1993-04-02

1995-12-26

Hille, Rolf

Active solid-state devices (e.g., transistors, solid-state diode

Bipolar transistor structure

With base region having specified doping concentration...

257587, 257588, H01L 2973, H01L 2970

Patent

active

054790476

ABSTRACT:
A modification of the self-aligned double poly fabrication process for bipolar transistors employs a thin sacrificial dielectric film to protect the wafer surface during the etching of an emitter opening through an overlying polysilicon contact layer. The sacrificial layer, which is preferably silicon dioxide for a silicon wafer, is thick enough to serve as an etch stop but thin enough to permit dopant from the polysilicon contact to be driven-in through the film to form an extrinsic base region. The dielectric film is left in place under the base contact polysilicon, but removed from the emitter area. It is preferably about 10-20 Angstroms thick when implemented as a silicon dioxide film. With this material system, the extrinsic base drive-in is preferably performed either by a rapid isothermal anneal at about 1,000.degree. C. for about 30-40 seconds, or in a furnace at about 975.degree. C. for about 10 minutes.

REFERENCES:
patent: 4157269 (1979-06-01), Ning et al.
patent: 4892837 (1990-01-01), Kudo
patent: 4910575 (1990-03-01), Komeda et al.
patent: 5148252 (1992-09-01), Taka
patent: 5175607 (1992-12-01), Ikeda
"Self-Aligned Bipolar Transistor for High-Performance and Low-Power-Delay VLSI", IBM Research Report, Nov. 17, 1980, pp. 1-14.

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