Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output addressing
Reexamination Certificate
2000-03-23
2003-08-19
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output addressing
C710S038000, C365S230060, C365S230020
Reexamination Certificate
active
06609160
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a selector which selects one particular output terminal out of a plurality of output terminals based on address signals that are input into a plurality of address terminals. More particularly, this invention relates to a selector which selects a plurality of output terminals in a specific group and outputs effective signals from the selected output terminals.
BACKGROUND OF THE INVENTION
FIG. 7
shows a conventional type of selector. Selector
100
shown in
FIG. 7
has a plurality of address terminals and a plurality of selector-output terminals. The selector
100
outputs an effective signal from only one of the plurality of selector-output terminals based on the address signal input from the address terminals. This figure shows an example in which address signals A
0
to A
3
are input into the selector
100
from four address terminals and one of the selector-output signals C
0
to C
9
that are output from
10
selector-output terminals is selected as an effective signal.
The selector
100
shown in
FIG. 7
is often used especially as a decoder such as a BCD (binary-coded decimal) decoder. There exists a relation such that the number of address terminals is less than the number of selector-output terminals. This relation generally holds in other decoders also. In the example shown in
FIG. 7
, the BCD code consisting of 4 bits is set as the address signals A
0
to A
3
and numerical values of 0 to 9 which represent the decimal numbers are assigned to the selector-output signals C
0
to C
9
, respectively.
Let us consider a specific example. When “0101” are input as the address signals A
0
to A
3
, only the selector-output signal C
5
is output as a signal having a logical level of “L”. All of the other selector-output signals C
0
to C
4
and C
6
to C
9
are output as signals having a logical level of “H”. Thus, it is possible to select, by using a small number of address terminals, one of the selector-output terminals that are formed with a larger number of terminals as compared to the number of address terminals, and output an effective signal from the terminal.
The selector
100
may be used as address decoder in memory management of a CPU. In this case, the address decoder receives an address signal from the CPU in order to identify one of the plurality of memory cells which are arranged in a matrix. The address decoder then selects a word line in the row direction and a bit line in the column direction to identify the location of the memory cell based on the address indicated by this address signal. Further, the address decoder outputs effective signals to these lines. Writing or reading data in or from the memory cell in its effective state is then performed via a sense amplifier or an I/O port.
Such selector (or decoder), however, selects only one of the plurality of selector-output signals in response to input of the address signal, and outputs the selected signal as effective signal. Therefore, when it is desired to output effective signals to some of the plurality of selector-output terminals, it is required to identify addresses one by one.
Especially, when the selector is used as the address decoder as mentioned above, the address decoder has such restriction that only a pair of word line and bit line can be selected for one address. Therefore, when it is desired to write the same data in a plurality of memory cells, it is required to prepare addresses one by one to identify each of these memory cells.
In this case, the processing of writing data becomes redundant, and such redundant processing wastefully occupies the CPU for a long period of time. Not only is the processing for other tasks affected by this wasteful occupation, but also there occurs such a problem that the program for memory to be executed by the operating system becomes complicated.
In addition, the conventional type of selector
100
further requires some other device such as a driver IC when it is desired to acquire a plurality of effective signals for one address.
SUMMARY OF THE INVENTION
It is an object of this invention to provide a selector which can select and output a plurality of effective signals at a time.
The selector according to one aspect of this invention comprises a plurality of selector-output terminals that are objects to be selected and a plurality of address terminals that select these selector-output terminals. The selector further comprises a plurality of group identification terminals that divide the selector-output terminals into groups, and enable selection of the selector-output terminals in each group. Therefore, it is possible to output effective signals from a plurality of selector-output terminals at a time based on the address signals that are input into the address terminals and the group identification signals that are input into the group identification terminals.
The selector according to another aspect of this invention comprises a plurality of selector-output terminals that are objects to be selected and a plurality of address terminals that select these selector-output terminals. The selector further comprises a plurality of group identification terminals that divide the selector-output terminals into groups, and enable selection of the selector-output terminals in each group. In addition, there is provided a selection output terminal that outputs a selection signal to discriminate between selector-output signals that are output from the selector-output terminal. Therefore, it is possible to select one or any group of a larger number of objects to be selected by making effective use of the limited number of selector-output terminals.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.
REFERENCES:
patent: 4833542 (1989-05-01), Hara et al.
patent: 5267212 (1993-11-01), Takashima
patent: 6271806 (2001-08-01), Motoshima et al.
Kunio Inukai, “Latest TTLIC Standard List, 1979 Edition”, edited by Kunio Inukai, published by CQ Publishing Co., Ltd., p. 124.
Fourie Inc.
Gaffin Jeffrey
Schneider Joshua D
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