Selectively reducing the number of cell evaluations in a...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000, C703S014000

Reexamination Certificate

active

11015491

ABSTRACT:
An electrical circuit comprising a plurality of cells can be simulated to produce simulation results by sorting cells between active status cells and inactive status cells and reducing the processing of simulation results from inactive cells to thereby save simulation time.

REFERENCES:
patent: 6389379 (2002-05-01), Lin et al.
Razdan et al., “Exploitation of Periodicity in Logic Simulation of Synchronous Circuits.”Proceedings of the International Conference on Computer Aided Design, 1990.
Takamine et al., “Clock Event Suppression Algorithm of VELVET and its Application to S-820 Development.”Proceedings of the 25th ACM/IEEE Conference on Design Automation, Jun. 1988.
Ulrich, “A Design Verification Methodology Based on Concurrent Simulation and Clock Suppression.”Proceedings of the Twentieth Design Automation Conference, Jun. 1983.
Ulrich et. al., “Design Verification for Very Large Networks Based on Concurrent Simulation and Clock Suppression.”IEEE International Conference on Computer Design(ICCD), Jun. 1983.
Ulrich, “Exclusive Simulation of Activity in Digital Networks.”Communications of the ACM, vol. 12 Issue 2, Feb. 1969.
Ulrich and Hebert, “Speed and Accuracy in Digital Network Simulation Based on Structural Modeling.”Proceedings of the Nineteenth Design Automation Conference, Jun. 1982.
Weber et al., “High Performance Simulation Techniques for Digital Systems: Periodic Signal Suppression in a Concurrent Fault Simulator.”Proceedings of the Conference on European Design Automation, Feb. 1991.

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