Selectively performing fetches for store operations during...

Details Selectively performing fetches for store operations during... Selectively performing fetches for store operations during...

2007-10-02

2007-10-02

Bragdon, Reginald (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S130000

Reexamination Certificate

active

11083264

ABSTRACT:
One embodiment of the present invention provides a processor which selectively fetches cache lines for store instructions during speculative-execution. During normal execution, the processor issues instructions for execution in program order. Upon encountering an instruction which generates a launch condition, the processor performs a checkpoint and begins the execution of instructions in a speculative-execution mode. Upon encountering a store instruction during the speculative-execution mode, the processor checks an L1 data cache for a matching cache line and checks a store buffer for a store to a matching cache line. If a matching cache line is already present in the L1 data cache or if the store to a matching cache line is already present in the store buffer, the processor suppresses generation of the fetch for the cache line. Otherwise, the processor generates a fetch for the cache line.

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patent: 6925524 (2005-08-01), Chow et al.
patent: 2002/0199070 (2002-12-01), Chaudhry et al.
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patent: WO 03/001383 (2003-01-01), None
John Hennessy and David Patterson, Computer Architecture A Quantitative Approach, 1996, Morgan Kaufman Publishers, Second Edition, pp. 677-685.
“MIPS R10000 Microprocessor User's Manual”, Version 2.0, Oct. 10, 1996, XP-002387380, p. 22.

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