Selectively inclusive cache architecture

Details Selectively inclusive cache architecture Selectively inclusive cache architecture

2006-08-14

2009-06-23

Lane, Jack A (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S122000, C711S124000

Reexamination Certificate

active

07552288

ABSTRACT:
In one embodiment, the present invention includes a method for maintaining data in a first level cache non-inclusively with data in a second level cache coupled to the first level cache. At the same time, at least a portion of directory information associated with the data in the first level cache may be maintained inclusively with a directory portion of the second level cache. Other embodiments are described and claimed.

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U.S. Appl. No. 11/503,633, filed Aug. 14, 2006, entitled, “Providing Quality Of Service (QoS) For Cache Architectures Using Priority Information,” by Li Zhao, Ravishankar Iyer, Ramesh Illikkal, Srihari Makineni and Donald Newell.
U.S. Appl. No. 11/513,554, filed Aug. 31, 2006, entitled, “Selective Storage Of Data in Levels Of A Cache Memory,” by Srihari Makineni, Jaideep Moses, Ravishankar Iyer, Ramesh Illikkal, Donald Newell and Li Zhao.
U.S. Appl. No. 11/087,916, filed Mar. 22, 2005, entitled “A Cache Eviction Technique For Reducing Cache Eviction Traffic” by Christopher J. Shannon, et al.
U.S. Appl. No. 10/897,474, filed Jul. 23, 2004, entitled “A Cache Eviction Technique for Inclusive Cache Systems” by Christopher J. Shannon, et al.
U.S. Appl. No. 11/374,222, filed Mar. 13, 2006, entitled “Synchronizing Recency Information In An Inclusive Cache Hierarchy” by Christopher J. Shannon, et al.

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