Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2005-09-13
2005-09-13
Brewster, William M. (Department: 2823)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S780000, C438S781000, C438S783000
Reexamination Certificate
active
06943121
ABSTRACT:
An inter-layer dielectric structure and method of making such structure are disclosed. A composite dielectric layer, initially comprising a porous matrix and a porogen, is formed. Subsequent to other processing treatments, the porogen is decomposed and removed from at least a portion of the porous matrix, leaving voids defined by the porous matrix in areas previously occupied by the porogen. The resultant structure has a desirably low k value as a result of the porosity and materials comprising the porous matrix and porogen. The composite dielectric layer may be used in concert with other dielectric layers of varying porosity, dimensions, and material properties to provide varied mechanical and electrical performance profiles.
REFERENCES:
patent: 6528409 (2003-03-01), Lopatin et al.
patent: 6770537 (2004-08-01), Farrar
patent: 2003/0004218 (2003-01-01), Allen et al.
patent: 2003/0057414 (2003-03-01), Dalton et al.
patent: 2004/0061229 (2004-04-01), Moslehi
Barns Chris E.
Gracias David H.
Kloster Grant M.
Leu Jihperng
Moon Peter K.
Blakely , Sokoloff, Taylor & Zafman LLP
Brewster William M.
Intel Corporation
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