Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2000-03-21
2002-06-11
Yoo, Do Hyun (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S157000, C711S155000, C711S156000, C365S189020, C365S230020
Reexamination Certificate
active
06405293
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to computer memory systems, and more particularly the invention relates to data storage, data access, and data update in a memory system.
In computer systems memory must be provided for the continuous storage, update, and access of digital data. For example, the configuration of hardware in a computer system can be controlled by digital data or parameters stored in memory and periodically accessed for configuration and reconfiguration of the hardware. Typically, while a parameter is being used for hardware configuration, a new parameter is being stored for future hardware reconfiguration. This is often accomplished in two banks of memory which toggle between a read mode and a write mode.
Heretofore, the access of two banks of memory for alternating reading and writing of hardware parameters or other data has required complex circuitry. The present invention is directed to a more efficient method and apparatus for memory access and continually reading and writing data.
SUMMARY OF THE INVENTION
In accordance with the invention, two banks of memory are coupled to a first interface terminal provided for reading data from the two banks of memory and to a second interface terminal provided for writing data to the two banks of memory. The two terminals are coupled through multiplexers to selectively connect to either the first memory or to the second memory for accessing and writing data.
In one embodiment the stored data is hardware configuration parameters which are accessed for hardware control and updated by a processor for reconfiguration of the hardware.
In a preferred embodiment, a first multiplexer selectively applies the first terminal and the second terminal to the first memory bank, a second multiplexer selectively applies the first terminal and the second terminal to the second memory bank, a third multiplexer selectively applies the outputs of the first memory bank and the second memory bank to the first terminal, and a fourth multiplexer selectively applies the outputs of the first memory bank and the second memory bank to the second terminal. A control register responds to an operation code and directs the multiplexers in accessing the two banks of memory for read and write operations.
The invention and objects and features thereof will be more readily apparent from the following detailed description and appended claims when taken with the drawing.
REFERENCES:
patent: 5570320 (1996-10-01), Runas
patent: 5737578 (1998-04-01), Hennenhoefer
patent: 6266751 (2001-06-01), Niescier
patent: 6288955 (2001-09-01), Shibano
patent: 6295571 (2001-09-01), Scardamalia
Chiang Kevin
Jen Scott Li-Huan
Wu Shengquan
McLean Kimberly N.
Oak Technology, Inc.
Woodward Henry K.
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