Adhesive bonding and miscellaneous chemical manufacture – Delaminating processes adapted for specified product – Delaminating in preparation for post processing recycling step
Patent
1989-04-17
1990-04-24
Powell, William A.
Adhesive bonding and miscellaneous chemical manufacture
Delaminating processes adapted for specified product
Delaminating in preparation for post processing recycling step
156626, 156650, 156656, 1566591, 357 67, 437192, 437246, H01L 2348, B44C 122, C23F 102
Patent
active
049204033
ABSTRACT:
Methods of fabricating metal interconnection lines in an integrated circuit. In general, one method comprises the steps of depositing a layer of metal on an inter-dielectric oxide layer. The layer of metal is patterned and etched to form metal interconnection lines over the oxide layer. Tungsten is selectively deposited onto the etched layer to completely form the metal interconnection lines. Additionally, in a second method, a layer of tungsten may be deposited prior to the layer of metal. This forms a metal line that is completely encapsulated in tungsten. In addition, selective tungsten employed to repair broken metal lines in a fabricated integrated circuit. The selective tungsten is deposited using a chemical vapor deposition process and is deposited onto masked and etched second level (or higher) metal lines formed in the integrated circuit. The method of selectively depositing tungsten comprises the steps of exposing the metal interconnection lines to a mixture of SiH.sub.4 at a rate between 3-10 standard cubic centimeters per minute, WF.sub.6 at a rate between 3-25 standard cubic centimeters per minute, and H.sub.2 at a rate between 25-100 standard cubic centimeters per minute. Then the exposed metal interconnection lines are processed at a pressure between 50-200 m Torr, a temperature between 250-350 degrees Celsius, and a deposition rate between 2000-10000 Angstroms per minute to form the fully interconnected metal lines. The present method improves the yields of multi-level metal integrated circuits and maximizes the potential gate usage therein. The conformal deposition of selective tungsten enhances the yields of integrated circuits and tungsten capping on aluminum metal lines, for example provides for a better electromigration resistance interconnection.
REFERENCES:
patent: 4517225 (1985-05-01), Broadbent
patent: 4648175 (1987-03-01), Metz et al.
patent: 4666737 (1987-05-01), Gimpelson et al.
Chin Maw-Rong
Chow Yu C.
Liao Kuan Y.
Rhoades Charles S.
Denson-Low Wanda K.
Gudmestad Terje
Hughes Aircraft Company
Powell William A.
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