Selective trim and wafer testing of integrated circuits

Details Selective trim and wafer testing of integrated circuits Selective trim and wafer testing of integrated circuits

2005-03-29

2005-03-29

Nguyen, Tuan H. (Department: 2813)

Semiconductor device manufacturing: process

With measuring or testing

C438S015000

Reexamination Certificate

active

06872582

ABSTRACT:
A method of selective trim and wafer testing of precision integrated circuits is provided by determining if a sample die is within specification. If so the sample parameters are measured and if the die passes the sample parameters the die is good and repeat the steps of determining if the die is within specification and measuring the sample parameters until a die fails the measurement test or requires a trimming and if a die fails a measurement test or requires trimming perform 100 percent test and trim.

REFERENCES:
patent: 6472897 (2002-10-01), Shyr et al.

Affiliated with

Also associated with

Rating

Selective trim and wafer testing of integrated circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Selective trim and wafer testing of integrated circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Selective trim and wafer testing of integrated circuits will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3395594