Selective timer control during single-step instruction...

Details Selective timer control during single-step instruction... Selective timer control during single-step instruction...

2007-01-30

2010-11-09

Le, Dieu-Minh (Department: 2114)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S055000

Reexamination Certificate

active

07831862

ABSTRACT:
A processing device includes a timer and a processor core configured to execute an instruction during a debug session. The processing device further includes a timer control module configured to selectively enable/disable the timer based on a characteristic of the instruction. Another processing device includes a timer, a processor core configured to single step execute a sequence of instructions during a debug session, and a timer control module configured to selectively enable/disable the timer during single step execution of each instruction of the sequence of instructions.

REFERENCES:
patent: 4090239 (1978-05-01), Twibell et al.
patent: 4926319 (1990-05-01), Wilkie et al.
patent: 5392052 (1995-02-01), Eberine
patent: 5541943 (1996-07-01), Niescier et al.
patent: 5568649 (1996-10-01), MacDonald et al.
patent: 5740451 (1998-04-01), Muraki et al.
patent: 5751735 (1998-05-01), Tobin et al.
patent: 5812830 (1998-09-01), Naaseh-Shahry et al.
patent: 6145103 (2000-11-01), Typaldos et al.
patent: 6553513 (2003-04-01), Swoboda et al.
patent: 6601189 (2003-07-01), Edwards et al.
patent: 6658555 (2003-12-01), Kahle et al.
patent: 6839654 (2005-01-01), Rollig et al.
patent: 6986026 (2006-01-01), Roth et al.
patent: 7073097 (2006-07-01), Kuwayama
patent: 7159144 (2007-01-01), Babu et al.
patent: 7162410 (2007-01-01), Nemecek et al.
patent: 7334161 (2008-02-01), Williams et al.
patent: 2003/0126502 (2003-07-01), Litt
patent: 2004/0260913 (2004-12-01), Babu et al.
patent: 2006/0117224 (2006-06-01), Wu
patent: 2007/0053301 (2007-03-01), Maruoka et al.
patent: 2007/0198759 (2007-08-01), Agarwal
patent: 2008/0184055 (2008-07-01), Moyer et al.
patent: 2008/0184056 (2008-07-01), Moyer et al.
patent: 2008/0320290 (2008-12-01), Moyer
patent: 06044086 (1994-02-01), None
patent: 06131271 (1994-05-01), None
patent: 10307737 (1997-11-01), None
patent: 2002063072 (2002-02-01), None
“MC68HC912D60A/D”, Rev. 3.1, Freescale Semiconductor, Inc., Aug. 2005, pp. 74-77; 140; 168-174; 223-262; 379-403.
U.S. Appl. No. 11/668,780, Office Action mailed May 4, 2009.
U.S. Appl. No. 11/765,891 Office Action mailed Sep. 30, 2009.
U.S. Appl. No. 11/765,891, Final Office Action mailed Mar. 4, 2010, 14 pages.
U.S. Appl. No. 11/668,780, Notice of Allowance mailed Nov. 13, 2009, 6 pages.
U.S. Appl. No. 11/668,780, Office Action mailed Apr. 5, 2010, 15 pages.
KIPO International Search Report mailed Oct. 28, 2010 for PCT/US08/64200, 2 pages.
Notice of Allowance mailed Aug. 10, 2010 for U.S. Appl. No. 11/668,780, 6 pages.
Notice of Allowance mailed Jul. 9, 2010 for U.S. Appl. No. 11/765,891, 6 pages.

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