Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2007-02-27
2007-02-27
Peikari, B. James (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
Reexamination Certificate
active
11250443
ABSTRACT:
A cache memory device with a cache section, which is provided between a CPU and a main memory and operates as a fast buffer memory, has a capability of storing input data in the cache section when attribute information affixed to the input data indicates a predetermined attribute.
REFERENCES:
patent: 5398245 (1995-03-01), Harriman, Jr.
patent: 5666484 (1997-09-01), Orimo et al.
patent: 5745728 (1998-04-01), Genduso et al.
patent: 5963981 (1999-10-01), Martin
patent: 6032190 (2000-02-01), Bremer et al.
patent: 6480936 (2002-11-01), Ban et al.
patent: 6502135 (2002-12-01), Munger et al.
patent: 6526483 (2003-02-01), Cho et al.
patent: 6539460 (2003-03-01), Castelli et al.
Intel, “Pentium Processor User's Manual vol. 2: 82496 Cache Controller and 82491 Cache SRAM Data Book”, Intel Corp. 1993, pp. 1-9, 1-14, 2-1, 3-8, and 4-5 to 4-6.
McGinn IP Law Group PLLC
NEC Electronics Corporation
Peikari B. James
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