Selective salicidation process for electronic devices...

Details Selective salicidation process for electronic devices... Selective salicidation process for electronic devices...

1999-12-28

2003-08-05

Wilczewski, Mary (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S649000, C438S656000, C438S660000, C438S683000

Reexamination Certificate

active

06602774

ABSTRACT:

TECHNICAL FIELD
This invention relates to a selective silicidation process for electronic devices integrated on a semiconductor substrate, and more particularly for electronic devices including a plurality of active elements formed with gate regions having at least one polysilicon layer, and for non-volatile electronic memory devices having multiple active elements formed with gate and drive regions having at least one polysilicon layer.
BACKGROUND OF THE INVENTION
The invention relates in particular, but not exclusively, to a selective silicidation process for the active elements of an EPROM or Flash EPROM cell, and the description to follow will consider this field of application for convenience of explanation.
Non-volatile memory devices integrated on a semiconductor substrate comprise matrices of memory cells where each cell includes a floating gate MOS transistor; and control circuitry including fast-logic MOS transistors.
Each floating gate MOS transistor conventionally comprises a drain region and a source region which are formed in the semiconductor substrate and separated by a channel region. A floating gate electrode is formed over the substrate and isolated therefrom by a thin layer of gate oxide. A control electrode is capacitively coupled to the floating gate electrode through a dielectric layer.
Each matrix of memory cells is organized into rows, known as the word lines, and columns, known as the bit lines. Cells belonging to the same word line have a common supply line which drives their respective control electrodes, and cells belonging to the same bit line have their drain terminals in common.
When memory devices of very small size are formed, the interconnect lines between the gate electrodes, which may be on the order of 0.25 um, for example, include layers of a low resistivity material.
Prior solutions for providing the low resistivity material layers have used composite material layers, known as silicides, which include silicon and a transition metal such as titanium, to cover those areas where resistivity is to be lowered.
Formation of a silicide layer over the active areas of MOS transistors comprises the following steps, following the formation of the transistor gate: implanting source and drain regions of the transistor; depositing a transition metal; and subjecting the transition metal to a thermal process for selectively reacting it with the substrate surface and producing the silicide layer.
This prior art method has problems when applying the thermal process for reacting the transition metal layer with the substrate surface in order to produce the silicidation of the implanted source and drain regions. Because a surface layer of the substrate is consumed, some of the dopant in the substrate leaks into the silicide layer. Accordingly, the silicide layer may become short-circuited to the substrate, thereby interfering with the normal operation of the cell.
SUMMARY OF THE INVENTION
Embodiments of the invention provide a silicidation process for the gate electrodes of electronic devices, specifically memory devices, having such features that the formation of a silicide layer over the implanted regions in the semiconductor substrate can be prevented, thereby overcoming the drawbacks with which prior art silicidation processes have been beset.
Therefore embodiments of the invention provide an improved process flow for silicidizing electronic devices which includes, before the silicidation step, a step of forming a dielectric layer to cover all the areas where the silicidation process may be critical and only leaving uncovered only those polysilicon portions where silicidation is instead desirable, without introducing any additional masking steps in the process.
Presented is a selective silicidation process for electronic devices integrated on a semiconductor substrate that include more than one of active elements formed with gate regions having at least one polysilicon layer. The process begins with depositing a dielectric layer over the entire surface of the semiconductor. Next the dielectric layer is removed to expose the polysilicon layer of the gate regions. A layer of a transition metal is deposited and subjected to a thermal treatment for selectively reacting it with the polysilicon layers and producing a silicide layer over the gate regions.
The features and advantages of a process according to the invention will be apparent from the following description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings.


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