Selective method to form roughened silicon

Details Selective method to form roughened silicon Selective method to form roughened silicon

1998-06-08

2002-03-12

Whitehead, Jr., Carl (Department: 2822)

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

C438S253000, C438S254000, C438S255000, C438S396000, C438S397000, C438S563000

Reexamination Certificate

active

06355536

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor fabrication and in particular, to a method of selectively forming silicon having a desired surface roughness.
BACKGROUND OF THE INVENTION
As DRAM's increase in memory cell density, there is a continuous challenge to maintain a sufficiently high storage capacitance despite decreasing cell area. It is important that storage node capacitor cell plates be large enough to retain an adequate charge or capacitance in spite of parasitic capacitances and noise which may be present during circuit operation. The principal way of retaining high cell capacitance with increasing cell density is through cell structure techniques. Such techniques include three dimensional cell capacitors, such as trenched or stacked capacitors.
One way of increasing capacitance is to roughen the interfacing surfaces of the capacitor, thereby maximizing the surface area for stored capacitance. According to one method, the surface of a polycrystalline silicon is coated with spin-on-glass (SOG) containing photoresist particles. With the photoresist particles acting as a micromask, etching provides a micro roughness on the surface of the polycrystalline silicon film, thereby increasing the effective surface area of the polycrystalline silicon film. See “Capacitance-Enhanced Stacked-Capacitor with Engraved Storage Electrode for Deep Submicron DRAMS,”
Solid State Devices and Materials,
1989, pp. 137-140. However, in addition to the overall complexity of this method, this method requires strict control of the size of the resist particles, and the resist particles must be distributed at a uniform density at the time of the coating. Another method, described in U.S. Pat. No. 5,691,249, is based on the grain growth of silicon to produce micro roughness on the surface of a polycrystalline silicon layer. This is accomplished by depositing silicon on a substrate in accordance with a low pressure chemical vapor deposition (LPCVD) method or the like, carrying out the deposition at the temperature (referred to as transition temperature) at which the crystal state of the deposited film makes the transition from an amorphous phase to a polycrystalline phase. Alternatively, surface roughness is increased by a so called “seed and anneal” method whereby an amorphous silicon film is formed on a substrate in a vacuum or in an inert gas such as nitrogen gas, then subjecting the sample to a heating (annealing) treatment at a temperature above the transition temperature of the silicon, again in a vacuum or in an inert gas such as nitrogen gas. However, techniques based on the grain growth of silicon to produce micro roughness on the surface of a polycrystalline silicon layer result in some deposition of silicon atoms over the entire surface of the silicon substrate surface. In certain instances, deposition of silicon atoms over the entire surface of the silicon substrate surface is undesirable, such as, for example, in the fabrication of capacitors, where silicon deposits between storage nodes may cause shorts or conductive paths from one storage node to the next. In addition, because these methodologies selectively create polycrystalline silicon structures, it is necessary that the silicon storage nodes be comprised of amorphous silicon prior to being subjected to these methodologies.
Therefore, the need remains for a method of forming silicon storage nodes on silicon substrates, wherein the silicon storage nodes have a roughened surface which does not result in deposition of silicon atoms over the entire surface of the silicon substrate. Further, there also remains a need for a method of forming silicon storage nodes on silicon substrates which does not require the silicon storage nodes to be comprised of amorphous silicon prior to being subjected to the surface-roughening treatment.
SUMMARY OF THE INVENTION
That need is met by the present invention by providing a method of forming silicon storage nodes on silicon substrates, wherein the silicon storage nodes have a roughened surface, which does not result in deposition of silicon atoms over the entire surface of the silicon substrate and which does not require the silicon storage nodes to be comprised of amorphous silicon prior to being subjected to surface-roughening treatment.


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T. Mine, S. Iijima, J. Yugami, K. Ohga and T. Morimoto, “Capacitance-Enhanced Stacked-Capacitor with Engraved Storage Electrode for Deep Submicron DRAMSs”, 1989, pp. 137-140.

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