Selective metal via plug growth technology for deep sub-micromet

Details Selective metal via plug growth technology for deep sub-micromet Selective metal via plug growth technology for deep sub-micromet

1995-05-24

1996-07-23

Mintel, William

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257774, 257775, H01L 2348

Patent

active

055392474

ABSTRACT:
Metal pillars (18) having diameters of less than about 1.0 .mu.m are grown in vias (16) in dielectric layers (14) between metal layers (12, 22) by a process comprising: (a) forming a first metal layer (12) at a first temperature and patterning the metal layer; (b) forming the dielectric layer to encapsulate the first patterned metal layer, the dielectric layer having a compressive stress of at least about 100 MegaPascal and being formed at a second temperature; (c) opening vias in the dielectric layer to exposed underlying portions of the patterned metal layer, the vias being less than about 1.0 .mu.m in diameter; (d) heating the semiconductor wafer at a temperature that is greater than either the first or second temperatures to induce growth of metal in the vias from the metal layer; and (e) forming the second metal layer (22) over the dielectric layer to make contact with the metal pillars.

REFERENCES:
patent: 4968643 (1990-11-01), Mukai

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