Selective loading of configuration data into configuration...

Details Selective loading of configuration data into configuration... Selective loading of configuration data into configuration...

2008-08-05

2009-08-25

Cho, James (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S040000

Reexamination Certificate

active

07579865

ABSTRACT:
In one embodiment, a programmable logic device (PLD) such as a field programmable gate array (FPGA) includes a non-volatile memory adapted to store a first bit, a second bit, and a plurality of configuration data. A plurality of configuration memory cells within the PLD is adapted to receive configuration data transferred from the non-volatile memory. The PLD further includes control logic adapted to determine based on the logic states of the first and second bits stored in the non-volatile memory and prior to any transfer of the configuration data whether to transfer the configuration data from the non-volatile memory to the configuration memory cells.

REFERENCES:
patent: 6981091 (2005-12-01), Shimanek et al.
patent: 7190190 (2007-03-01), Camarota et al.
patent: 7411417 (2008-08-01), Rutledge et al.

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