Selective latency reduction in bridge circuit between two busses

Details Selective latency reduction in bridge circuit between two busses Selective latency reduction in bridge circuit between two busses

1996-09-26

1999-11-02

Sheikh, Ayaz R.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

710128, 710101, 710 9, 710 3, 710 57, 713400, G06F 1338

Patent

active

059788780

ABSTRACT:
A bridge circuit passes digital information between a primary PCI bus and a secondary PCI bus with increased throughput. The PCI busses carry digital information using respective clock signals having a known minimum skew therebetween. The interface bridge circuit includes primary and secondary PCI bus interfaces configured and arranged to communicate with the primary and secondary PCI busses respectively, and a memory buffer configured and arranged to store the digital information and to be accessed by the primary and secondary PCI bus interfaces. Further, a programmable configuration register is configurable in response to digital configure information received from the primary bus, and is adapted to provide an enable signal to one of the primary PCI bus interface and the secondary PCI bus interface. The enable signal indicates that the digital information is ready in the memory buffer for access by the one of the primary PCI bus interface and the secondary PCI bus interface.

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