Selective interrupt delivery to multiple processors having...

Details Selective interrupt delivery to multiple processors having... Selective interrupt delivery to multiple processors having...

2005-12-13

2005-12-13

Dang, Khanh (Department: 2111)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output access regulation

C710S266000, C710S303000

Reexamination Certificate

active

06976099

ABSTRACT:
A method of and apparatus for selective delivery of an interrupt to one of multiple processors having independent operating systems is described. The interrupts are generated from various platform devices in the computer system. Depending on the mode of operation of the system, a controller is configured to deliver interrupts to a co-processor when the host processor is off, without turning on the host processor. The interrupt may be delivered to the correct processor using wither a bus-based message or a dedicated interrupt line.

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MultiProcessor Specification, Version 1.4, Intel Corporation, May 1997.

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