Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output access regulation
Reexamination Certificate
2000-09-29
2004-08-03
Dang, Khanh (Department: 2111)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output access regulation
C710S266000, C710S303000
Reexamination Certificate
active
06772241
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of computer systems and, in particular, to the operation of computer systems having multiple independent processors.
BACKGROUND OF THE INVENTION
Computer systems typically include various platform devices (e.g., disk drive) that operate under the control of a central processing unit (CPU). During operation of the computer system, interrupts are generated by these platform devices and transmitted to the CPU in order to communicate with the CPU.
Over the last few years, there have been many advances in computer system technology. These advances have lead to the development of computer systems having multiple processors to support additional and/or enhanced computing features.
FIG. 1
illustrates, for example, one type of computer system that uses a co-processor in conjunction with a host CPU to perform complex mathematical operations. In such systems, the processors are under the control of a single operating system (OS). The use of single operating system, however, may limit the flexibility of the computer system.
Other advances in computer system technology have led to the development of battery-powered portable computers (e.g., laptop or notebook style computers, hand-held computers, etc.) that are implemented with high-speed processors similar to those implemented in desktop computers. Some of these portable computers may also include multiple processors. In order to conserve power in these systems, one or more of the processors may be placed in a low power mode, referred to as a “sleep mode” or “Limited ON” mode, when not in active use.
One problem with such a system is that the co-processor is not independent of the host CPU and, thus, cannot operate when the system is asleep. Therefore, the co-processor in the computer system will not be able to access system resources when the host processor is shut-down. In addition, when an interrupt is transmitted by a platform device, the interrupt is received by all the processors in the system including those that are not currently running or intentionally sitting idle. Such a configuration may lead to inefficiencies in the computer system. For example, a system operating with host CPU turned off may respond by waking up the host CPU upon receipt of an interrupt and, thereby, undesirably increase the power consumption of the system.
REFERENCES:
patent: 4679166 (1987-07-01), Berger et al.
patent: 4695945 (1987-09-01), Irwin
patent: 5282272 (1994-01-01), Guy et al.
patent: 5388215 (1995-02-01), Baker et al.
patent: 5495569 (1996-02-01), Kotzur
patent: 5511200 (1996-04-01), Jayakumar
patent: 5619705 (1997-04-01), Karnik et al.
patent: 5857090 (1999-01-01), Davis et al.
MultiProcessor Specification, Version 1.4, Intel Corporation, May 1997.
Buch Deep K.
Gamsaragan Edward
George Varghese
Pentkovski Vladimir M.
Zagacki Paul
Blakely , Sokoloff, Taylor & Zafman LLP
Dang Khanh
Intel Corporation
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