Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-11-12
2002-07-16
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S625000, C438S626000, C438S627000, C438S628000, C438S629000, C438S633000, C438S637000, C438S643000, C438S645000, C438S648000, C438S653000, C438S654000, C438S656000, C438S672000, C438S675000, C438S678000, C438S687000
Reexamination Certificate
active
06420258
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
It is a general object of the present invention to provide a new and improved method of forming an integrated circuit in which special copper interconnects are formed by a combination of physical vapor deposition (PVD) and electrochemical copper deposition (ECD) techniques. By said techniques, high aspect ratio vias and trenches can be filled with copper which is electromigration resistant since interconnects are chemical mechanical polished (CMP) back without dishing effects yielding full cross-sectional lines.
As a background to the current invention, the requirement of lower resistance material has been more stringent as the device dimensions approach micron and sub-micron design ground rules. Pure copper metal lines have been one of the best choices because of copper's low resistivity and high conductivity. This invention describes the formation of copper films by using a combination of physical vapor deposition (PVD) and electrochemical copper deposition (ECD) techniques. By said techniques, high aspect ratio vias and trenches can be filled with copper without the problem of dishing.
(2) Description of Related Art
The present invention is a new and improved method for fabricating special copper films by using a combination of physical vapor deposition (PVD) and electrochemical copper deposition (ECD) techniques. By said techniques, high aspect ratio vias and trenches can be filled with copper. High conductivity, low resistivity conducting metal lines are important in fabricating quarter micron and below semiconductor devices. The related Prior Art background patents will now be described in this section. These related Prior Art patents are presented with the most recent art described first.
U.S. Pat. No. 5,891,804 entitled “Process for Conductors with Selective Deposition” granted Apr. 6, 1999 to Havermann and Stoltz describes a selective copper deposition using various initiator metals. A method of forming a conductor on an interlevel dielectric layer which is over an electronic microcircuit substrate is described. The method utilizes: forming an intralevel dielectric layer over the interlevel dielectric layer; forming a conductor groove in the intralevel dielectric layer exposing a portion of the interlevel dielectric layer; anisotropically depositing a selective deposition initiator onto the intralevel dielectric layer and onto the exposed portion of the interlevel dielectric layer; and selectively depositing conductor metal to fill the groove to at least half-full. The selective deposition initiator may selected from the group consisting of tungsten, titanium, palladium, platinum, copper, aluminum, and combinations thereof. In one embodiment, the selective deposition initiator is palladium, and the selectively deposited conductor metal is principally copper.
U.S. Pat. No. 5,824,599 entitled “Protected Encapsulation of Catalytic Layer for Electroless Copper Interconnect” granted Oct. 20, 1998 to Schacham-Diamand et al shows a selective electroless deposition for a copper interconnect. Once a via or a trench is formed in a dielectric layer, a titanium nitride (TiN) or tantalum (Ta) barrier layer is deposited. Then, a catalytic copper seed layer is conformally blanket deposited in vacuum over the barrier layer. Next, without breaking the vacuum, an aluminum protective layer is deposited onto the catalytic layer to encapsulate and protect the catalytic layer from oxidizing. An electroless deposition technique is then used to auto-catalytically deposit copper on the catalytic layer. The electroless deposition solution dissolves the overlying protective layer to expose the surface of the underlying catalytic layer. The electroless copper deposition occurs on this catalytic surface, and continues until the via/trench is filled. Subsequently, the copper and barrier material are polished by an application of chemical-mechanical polishing (CMP) to remove excess copper and barrier material from the surface, so that the only copper and barrier material remaining are in the via/trench openings. Then an overlying silicon nitride (SiN) layer is formed above the exposed copper in order to form a dielectric barrier layer. The copper interconnect is fully encapsulated from the adjacent material by the TiN (or Ta) barrier layer and the overlying SiN layer.
U.S. Pat. No. 5,789,320 entitled “Plating of Noble Metal Electrodes for DRAM and FRAM” granted Aug. 4, 1998 to Andricacos et al describes a noble metal plating process on a preexisting seed layer which is used in the fabrication of electrodes for DRAM and FRAM. The plating may be spatially selective or nonselective. In the nonselective case, a blanket film is first plated and then patterned after deposition by spatially selective material removal. In the selective ease, the plated deposits are either selectively grown in lithographically defined areas by a through-mask plating technique, or selectively grown as a conformal coating on the exposed regions of a preexisting electrode structure. A diamond-like carbon mask can be used in the plating process. A self-aligned process is disclosed for selectively coating insulators in a through-mask process.
U.S. Pat. No. 5,429,987 entitled Method of Profile Control of Selective Metallization” granted Jul. 4, 1995 to Allen describes a selective copper deposition for forming interconnects. The method comprises: (a) depositing a selective nucleating layer on the dielectric layer; (b) depositing a sacrificial layer over the nucleating layer; (c) pattering the sacrificial layer and nucleating layer such that the resulting pattern of the nucleating layer and sacrificial layer is equivalent to the desired pattern of conductive lines (d) depositing a sidewall guide material over the patterned sacrificial and nucleating layers; (e) forming sidewall guides; (f) removing the sacrificial layer; and (g) depositing conductive material between the sidewall guides and on the nucleating layer. The nucleating layer may comprise titanium nitride, the sacrificial layer may comprise silicon dioxide, the sidewall guide material may comprise silicon nitride, and the conductive material may comprise copper. In another aspect of the invention, a layer of silicon nitride may be provided over the conductive material.
U.S. Pat. No. 5,112,448 entitled “Self-Aligned Process for Fabrication of Interconnect Structures in Semiconductor Applications” granted May 12, 1992 Chakravorty shows a seed layer deposition over polyimide steps. These polyimide steps are utilized to break electrical connection of the seed layer, so that electroplating of copper occurs only in the trenches. The method of fabricating conductors in dielectric trenches is performed in self-aligned manner. Interconnect modules with a high conductor density are achieved by using a copper-polyimide system as a versatile packaging approach. A photosensitive polyimide is applied to a substrate and lithographically patterned to form polyimide steps having a characteristic positive slope, between which are defined trenches in which the substrate is exposed. A thin electroplating seed layer is deposited over the polyimide steps and the substrate. Copper is electroplated into trenches, but does not plate onto the tops of the polyimide steps, since the electroplating seed layer at that location is not electrically connected to the electroplating seed layer in the bottom of the trenches. The electroplating seed layer on top of the polyimide steps is then removed by chemical etching, plasma machining, or ion-milling. A planar structure is eventually obtained without the use of multiple coatings of polyimide layers or any additional masking layers or lift-off layers.
U.S. Pat. No. 4,866,008 entitled “Method for Forming Self-Aligned Conductive Pillars on Interconnects” granted Sep. 12, 1989 to Brighton and Roane describes a via plug on an metal interconnect using a photoresist mask. Disclosed are methods of forming a self-aligned conductive pillar on an interconnect on a body having semi-conducting surfaces. A fi
Chen Sheng Hsiung
Tsai Ming-Hsing
Ackerman Stephen B.
Gurley Lynne
Niebling John F.
Saile George O.
Taiwan Semiconductor Manufacturing Company
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