Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Reexamination Certificate
2011-04-19
2011-04-19
Graybill, David E (Department: 2894)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
C438S424000, C438S700000, C438S702000, C438S703000, C438S763000, C257SE51040
Reexamination Certificate
active
07927961
ABSTRACT:
A disclosed selective etching method comprises mixing a polymer with carbon nanotubes, applying the mixture to an etching target layer to form a carbon nanotube-polymer composite layer, forming a hard mask by patterning the carbon nanotube-polymer composite layer, such that a part of the etching target layer is selectively exposed, and selectively etching the etching target layer exposed through the hard mask. The polymer preferably includes a photoresist. Also disclosed is a method for forming an isolation structure of a memory device using the selective etching method.
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English translation of JP10282649, translated on Aug. 14, 2010.
Graybill David E
Hynix / Semiconductor Inc.
Marshall & Gerstein & Borun LLP
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