Selective etching for improved dielectric interlayer planarizati

Details Selective etching for improved dielectric interlayer planarizati Selective etching for improved dielectric interlayer planarizati

1997-12-18

1999-12-28

Chaudhari, Chandra

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438625, 438624, 438633, H01L 21469

Patent

active

060081163

ABSTRACT:
Planarization of a dielectric interlayer containing a dielectric gap filled layer is improved and facilitated by selective etching to reduce or eliminate steps in the gap filled dielectric layer before oxide deposition and polishing. Embodiments include gap filling a patterned metal layer with SOG or HSQ, forming a photoresist mask with an opening over steps having a height greater than about 3,000 .ANG., etching to reduce the height of the step by at least 70% depositing silicon oxide derived from TEOS or silane by PECVD and CMP.

REFERENCES:
patent: 5663108 (1997-09-01), Lin
patent: 5888898 (1999-03-01), Ngo et al.

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