Selective epitaxy BiCMOS process

Details Selective epitaxy BiCMOS process Selective epitaxy BiCMOS process

1989-01-19

1990-05-29

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 63, 437 31, 437 33, 437228, 437 90, 357 43, H01L 21265

Patent

active

049295705

ABSTRACT:
A process for fabricating both bipolar and complementary field effect transistors in an integrated circuit is disclosed. The process begins with a structure having a P type substrate 10, an N type epitaxial layer 15, and an intervening N type buried layer 12. The process includes the steps of removing all of the epitaxial layer 15 and all of the buried layer 12 from regions of the substrate where NMOS devices are to be formed, to thereby leave second regions of the epitaxial layer 15 and buried layer 12 having sidewalls 21 protruding above the substrate 10. A layer of silicon dioxide 25 is formed at least over the sidewalls of the protruding regions, and then a further epitaxial deposition of silicon is employed to reform the epitaxial layer 28 over the first regions, which epitaxial layer 28 is separated from the previously formed epitaxial layer 15 by the silicon dioxide isolation 25. The process continues by fabricating bipolar and field effect transistors in separate ones of the first and second regions.

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