Selective deposition of double damascene metal

Details Selective deposition of double damascene metal Selective deposition of double damascene metal

2007-07-24

2007-07-24

Dang, Trung (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S674000, C438S675000, C438S687000, C257SE21579, C257SE21586

Reexamination Certificate

active

11364654

ABSTRACT:
A method has been disclosed that allows the selective deposition of the metal for double damascene silicon wafer processing. This selective deposition allows the metal to be deposited only in the via holes, contact holes, channels or where ever the deposition is targeted to be deposited on the wafer where it is needed. This method allows double damascene wafers to be processed with out the necessity of polishing back the whole surface of the wafer to remove metal from most of the wafer surface, as is currently the practice.

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patent: 6716743 (2004-04-01), Nagashima
patent: 6815336 (2004-11-01), Shue et al.
patent: 2004/0000489 (2004-01-01), Zhang et al.
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patent: 2006/0046455 (2006-03-01), Nitta et al.
patent: 2006/0115983 (2006-06-01), Fujii et al.

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