Selective cap layers over recessed polysilicon plugs

Details Selective cap layers over recessed polysilicon plugs Selective cap layers over recessed polysilicon plugs

2000-08-07

2002-09-24

Everhart, Caridad (Department: 2825)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S240000, C438S608000, C438S629000, C438S063000, C438S652000, C438S672000, C438S678000, C438S686000, C438S902000

Reexamination Certificate

active

06455424

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to integrated conductive plugs contacting semiconductor elements and, more particularly, to oxidation-resistant partial plugs (e.g., oxygen barriers and conductive oxides).
BACKGROUND OF THE INVENTION
Semiconductor devices formed in the surface region of a silicon wafer substrate each have multiple elements to be electrically connected to the surrounding circuitry and to each other. Some of these electrical connections extend through protective insulating layers that cover each device level to electrically isolate adjacent levels. The insulating layers typically provide planarized surfaces for subsequent semiconductor device fabrication. Insulating materials include borophosphosilicate glass (BPSG), oxide deposited from tetraethyl-orthosilicate (TEOS), newer low dielectric (low k) materials, etc.
For example, a memory cell in an integrated circuit, such as a dynamic random access memory (DRAM) array, typically comprises a charge storage capacitor (or cell capacitor) electrically connected to an access device such as a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET). The MOSFET applies or removes charge on the capacitor, thus affecting the logical state defined by the memory cell. After formation of the MOSFET device elements, a protective insulating layer of BPSG is typically deposited, through which electrical connection must then be made to the subsequently fabricated capacitors and wiring layers above the BPSG layer. It is important to maintain good ohmic electrical connections between the capacitors and the underlying device elements (e.g., drain region of a MOSFET), and to maintain these good ohmic contacts throughout the lifetimes of the integrated circuits. Moreover, the material that contacts the substrate must be compatible so as not to poison the active areas and disturb finely tailored electrical characteristics.
Typically, vertical connections are made by filling vias formed through insulating layers with conductive polycrystalline silicon (i.e., polysilicon or poly), thereby contacting the substrate. The resultant structure filling the via is often referred to as a “poly plug.”
In order to maintain a certain minimum charge storage as device dimensions are scaled down and packing densities increase, capacitors for DRAM devices are being developed for incorporation of dielectric materials having increased dielectric constants (k). Such high k materials include tantalum oxide (Ta
2
O
5
), barium strontium titanate (BST), strontium titanate (ST), barium titanate (BT), lead zirconium titanate (PZT) and strontium bismuth tantalate (SBT). These materials are characterized by effective dielectric constants significantly higher than conventional dielectrics (e.g., silicon oxides and nitrides). Whereas k equals about 3.9 for silicon dioxide, the dielectric constants of these new materials can range from 20 to 40 (tantalum oxide) to 300 (BST), and some even higher (600 to 800). Using such materials enables the creation of much smaller and simpler capacitor structures for a given stored charge requirement, enabling the packing density dictated by future circuit design.
Difficulties have been encountered, however, in incorporating these materials into fabrication process flows. For example, Ta
2
O
5
is deposited by chemical vapor deposition (CVD) employing organometallic precursors in a highly oxidizing ambient. Additionally, after deposition the material is annealed to remove carbon. This anneal is typically conducted in the presence of nitrous oxide (N
2
O), which is also highly oxidizing, while volatile carbon complexes are driven out.
Due to the oxidizing nature of the reactants and by-products for forming high-k materials, surrounding materials are subject to degradation. Similarly, formation of other high k materials often involves exposing adjacent materials to oxidizing or otherwise corrosive environments. Corrosion of the conductive materials forming the electrical connections to device elements reduces their conductivity, and has been viewed as a major obstacle to incorporating high-k materials into integrated circuits.
Accordingly, a need exists for improved contact plugs and methods of making the same.
SUMMARY OF THE INVENTION
The present invention is a method of selectively forming materials in conductive plugs in a manner that avoids etching the material. In the illustrated embodiments, a noble metal, preferably platinum, is incorporated into a cap to a conductive plug. In one embodiment, a sacrificial layer is deposited over a recessed silicon plug. The sacrificial layer is readily etched, particularly by chemical mechanical planarization, to isolate the material within a via. The layer is then replaced, preferably by immersion plating, with the noble metal. Alternatively, the refractory metal layer can be directly formed by selective deposition, particularly electroless plating, which does not require the formation of a sacrificial layer.
Thus, in accordance with one aspect of the invention, a method is provided for selectively forming a cap layer for a conductive plug. A via, exposing a semiconductor substrate, is formed in a semiconductor substrate. A partial plug then partially fills the via to directly contact the substrate. A sacrificial layer is deposited into the via, in electrical contact with the partial plug, and over the insulating layer. Excess sacrificial metal layer is removed from over the insulating layer. Atoms of the sacrificial metal layer within the via are replaced with atoms of a cap material.
In accordance with another aspect of the invention, a method is provided for fabricating an integrated circuit. The method includes filling a contact via in an integrated circuit with a silicon plug. The plug is recessed, and a plug cap including a noble metal is selectively formed over the recessed silicon plug without etching the noble metal. A capacitor is then formed over the plug cap, the incorporating high k dielectric material.
In accordance with another aspect of the invention, a process is provided for forming an integrated circuit memory cell. A recessed plug is formed within a via through an insulating layer. The recessed plug is thereby electrically connected to a transistor active area. A cap layer, comprising non-oxidizing material, such as an oxygen barrier or a conductive oxide, is selectively formed within the via over the recessed plug. A capacitor with a high dielectric constant material is then formed over the cap layer.
In accordance with another aspect of the invention, a method is provided for forming a plurality of non-oxidizing contact structures in an integrated circuit. The method includes forming a plurality of openings through an insulating layer, and then blanket depositing a sacrificial material over the insulating layer and into the openings. The sacrificial layer is etched to remove it from over the insulating layer outside the openings, and the sacrificial layer left inside the openings is replaced with a non-oxidizing material, such as an oxygen barrier or a conductive oxide.
In accordance with another aspect of the invention, a memory cell is provided in an integrated circuit. The cell includes a silicon partial plug that partially fills a via formed through an insulating layer. The partial plug contacts an underlying semiconductor substrate. A plug cap comprising a noble metal fills a top portion of the via over the partial plug. A capacitor with a high dielectric constant material is positioned over the plug cap.
In accordance with another aspect of the invention, an integrated circuit is provided with a conductive plug. The plug includes a partial plug that is compatible and in electrical contact with an underlying semiconductor substrate. A platinum-containing cap layer is aligned over the partial plug, making electrical contact with the partial plug. An insulating layer surrounds the partial plug and cap layer.


REFERENCES:
patent: 5099305 (1992-03-01), Takenaka
patent: 5111355 (1992-05-01), Anand et al.
patent: 5187638 (1993-02-01), Sandhu

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