Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2011-05-10
2011-05-10
Baderman, Scott T (Department: 2114)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S010000
Reexamination Certificate
active
07941698
ABSTRACT:
Processor operating methods and integrated circuits are described. According to one embodiment, an integrated circuit includes a processor configured to execute a first application and to redundantly execute a second application while executing the first application, the first application being different from the second application. According to another embodiment, a processor operating method includes receiving a request to execute an application using a processor having a plurality of processor cores. The method also includes, in response to the receiving, determining whether the application should be executed redundantly or non-redundantly, non-redundantly executing the application using one processor core of the plurality if the determining comprises determining that the application should be executed non-redundantly, and redundantly executing the application using two or more processor cores of the plurality if the determining comprises determining that the application should be executed redundantly.
REFERENCES:
patent: 7328371 (2008-02-01), Kalyanasundharam et al.
patent: 7711941 (2010-05-01), Henry et al.
patent: 2002/0046324 (2002-04-01), Barroso et al.
patent: 2002/0165961 (2002-11-01), Everdell et al.
patent: 2005/0015659 (2005-01-01), Pomaranski et al.
patent: 2005/0055608 (2005-03-01), Shidla et al.
patent: 2006/0123018 (2006-06-01), Ashok et al.
patent: 2006/0212677 (2006-09-01), Fossum
patent: 2007/0088979 (2007-04-01), Pomaranski et al.
patent: 2007/0277023 (2007-11-01), Weiberle et al.
patent: 2008/0148015 (2008-06-01), Takamoto et al.
patent: 2008/0148034 (2008-06-01), Henry et al.
patent: 2009/0070552 (2009-03-01), Kanstein et al.
patent: 2009/0089790 (2009-04-01), Manczak et al.
patent: 2009/0113240 (2009-04-01), Vera et al.
patent: 2009/0164767 (2009-06-01), Kanso et al.
patent: 2009/0164826 (2009-06-01), Kottke
patent: 2009/0240979 (2009-09-01), Campini et al.
patent: 2010/0004841 (2010-01-01), Mueller et al.
patent: WO 03050624 (2003-06-01), None
Aggarwal, Nidhi et al. “Configurable Isolation: Building High Availability Systems with Commodity Multi-Core Processors”, ISCA '07, Jun. 9-13, 2007.
Aggarwal, Nidhi et al. “Reconfiguration in a Multi-Core Processor System with Configurable Isolation”; U.S. Provisional Patent Application.
Bernick, David et al.“NonStop Advanced Architecture”; Proceedings of the 2005 International Conference on Dependable Systems and Networks (DSN '05), 2005 IEEE.
Bressoud, Thomas C. and Schneider, Fred B.“Hypervisor-Based Fault-Tolerance”; ACM Transactions on Computer Systems, vol. 14, No. 1. Feb. 1996, pp. 80-107.
Gold, Brian T. et al. “Truss: A Reliable, Scalable Server Architecture,” IEEE Nov./Dec. 2005 pp. 51-59.
Gomaa, M. et al., “Transient-Fault Recovery for Chip Multiprocessors,” International Symposium on Computer Architecture, 2003.
Kumar, Rakesh et al, “Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance”; In Proceedings of the 31st International Symposium on Computer Architecture, Jun. 2004.
Srinivasan, Jayanth et al. “The Impact of Technology Scaling on Lifetime Reliability”; Proceedings of “The International Conference on Dependable Systems and Networks (DSN-04),” Jun. 2004
U.S. Appl. No. 11/787,881 Inventor: Aggarwal, Nidhi et al., filed Apr. 17, 2007.
Aggarwal, Nidhi et al. “Altering a Degree of Redundancy Used During Execution of an Application”; U.S. Appl. No. 12/250,367, filed Oct. 13, 2008.
Aggarwal Nidhi
Jouppi Norman Paul
Ranganathan Parthasarathy
Baderman Scott T
Hewlett--Packard Development Company, L.P.
Ko Chae
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