Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-03-23
2002-05-07
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06385756
ABSTRACT:
BACKGROUND
1. Technical Field
The present invention relates generally to semiconductor devices; and, more particularly, it relates to functionality identification and selection within a semiconductor device.
2. Description of Prior Art
Semiconductor devices inherently have fixed and limited output pin budgets. That is to say, on any given die, there are a finite number of output pins that may be used for various purposes depending on the functionality of the semiconductor device. There exists an inherent design constraint in optimal allocation of these pins in a semiconductor device. Furthermore, there is a difficulty in accommodating a variety of devices having different functionality using a single die. The development of the semiconductor industry has led to an intrinsic bottleneck in device design, in that, while multiple and increased functionality density may now be achieved on the semiconductor device real estate that in previous years, there nevertheless still exists the limited number of input/output pins for the semiconductor device.
Compounding such problems, in typical, a conventional design solution is to reserve a number of General Purpose Input/Output (GPIO) pins in a given semiconductor device's design to permit quick response to a particular customer's needs for new features. These GPIOs may be reserved to correct functional problems of the semiconductor device. This reservation of sometimes numerous pins, on a device that is already limited in number of total available pins, presents a design trade-off in the semiconductor device's layout and implementation. For many customers, the reserved pins may go completely unused, sometimes significantly limiting the functionality of the semiconductor device. Semiconductor device design engineers are typically reluctant to surrender these GPIOs for uses that may not be used by a majority of customers. This inherently pin consumptive solution, in reserving multiple GPIOs, works against providing increased functionality for a semiconductor device. Furthermore, reserving multiple GPIOs can add package cost by forcing the semiconductor device to be housed in a package capable of containing the extra pins.
Two common conventional solutions are used to attempt to provide multiple functionality for a given semiconductor device having a finite number of available pins. One of the conventional solutions involves simply removing other pins after prioritizing the necessity of the pins to meet a majority of customer needs. Typically, the pins ranking near the lower end of the prioritization are GPIOs or power pins. Often several of the multiple power pins are eliminated in exchange for an internal common power plane throughout the device that is supplied via a single or reduced number of pins. This potentially reduces noise immunity by increasing the inductance and resistance of the semiconductor device's power plane relative to the printed circuit board's power plane. Certain conventional semiconductor devices exchange GPIO pins and use them for selecting functionality within the semiconductor device. A common implementation is the connection of the select pin to either an elevated potential or a ground potential. In addition, multiple select output pins can be multiplexed to provide for even increased functionality, e.g., two pins may be used to provide for four different functions, three pins to provide for eight, etc.
Another conventional solution implements bonding options within the internal real estate of the semiconductor device. A typical implementation of this employs multiple select pads that are connected to an elevated potential via a pull-up resistor. The pad that is used for selecting a particular function is down-bonded to the leadframe of the semiconductor device internally, and the leadframe is connected to an external ground potential. A distinct disadvantage is this conventional solution is the requirement to dedicate valuable real estate of the semiconductor device for these pull-up resistors; it is inherently space consumptive. Also, a special kind of bonding pad is required to accommodate the connection to the leadframe. Resistor tolerance issues and problems further complicate this conventional solution by the introduction of the pull-up resistors internal to the semiconductor device.
Further limitations and disadvantages of conventional and traditional systems will become apparent to one skilled in the art through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.
SUMMARY OF THE INVENTION
Various aspects of the present invention can be found in a functionality selection system that selects at least one function from a plurality of functions within a device. The device is commonly a semiconductor device capable of performing a plurality of functions. These functions are embedded in the semiconductor device. A function selector is employed that selects at least one function. If desired, one or more additional selectors select more than one function thereby providing a multi-functional semiconductor device. Furthermore, the one or more selectors collectively select one or more functions of the semiconductor device in certain embodiments of the invention.
The selector is a pad placed internal to the semiconductor device in one embodiment of the invention. The pad is strategically placed between a first pad having a first potential and a second pad having a second potential. The pad is bonded either to the first pad or the second pad. Alternatively, the pad is double bonded to a pin to which either the first pad or the second pad is bonded. The bonding of the pad to either the first pad, the second pad, or to the pin occurs prior to encapsulation of the semiconductor device.
In addition, various aspects of the present invention can be found in a device identification system that uses at least one function from a plurality of functions within a device. The semiconductor device having a certain functionality is placed within the device identification system for identification. The device identification system is used to identify and classify the semiconductor device.
Another aspect of the invention is found in a security system that couples a specific software to a specific hardware. In one embodiment, the invention serves as a key that ensures that the specific software is not loaded indiscriminately on just any given hardware. In other words, even though the semiconductor device is capable of many functions, by bonding a select pad in order to disable a function in the semiconductor device, the software will be prevented from running.
Another aspect of the invention is found in a method that selects at least one function from a plurality of functions within a device. The method involves a plurality of functions embedded in a device, and the method then selects at least one function from the plurality of functions. The selection of the at least one function is performed using a function selector. In certain embodiments of the invention, the function selector is a pad that is bonded to another pad having a ground or other voltage potential.
Another aspect of the invention is found in a method that identifies the device using the selected at least one function. In this embodiment, the semiconductor device is analyzed and classified using the selected at least one function.
Other aspects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.
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Robe et al, “A Sonet STS-3c User Network Interface Integrated Circuit,” IEEE, Jun. 1991, pp. 732-740.
Conexant Systems Inc.
Siek Vuthe
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