Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-09-29
2002-09-17
Smith, Matthew (Department: 2813)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C430S005000
Reexamination Certificate
active
06453457
ABSTRACT:
BACKGROUND OF THE INVENTION
1. The Field of the Invention
This invention relates to the field of printed feature manufacturing, such as integrated circuit manufacturing. In particular, this invention relates to automatically identifying evaluation points where errors are computed and analyzed to achieve improved agreement between a design layout and an actual printed feature.
2. Description of Related Art
To fabricate an integrated circuit (IC), engineers first use a logical electronic design automation (EDA) tool, also called a functional EDA tool, to create a schematic design, such as a schematic circuit design consisting of symbols representing individual devices coupled together to perform a certain function or set of functions. Such tools are available from CADENCE DESIGN SYSTEMS and from SYNOPSYS. The schematic design must be translated into a representation of the actual physical arrangement of materials upon completion, called a design layout. The design layout uses a physical EDA tool, such as those available from CADENCE and AVANT!. If materials must be arranged in multiple layers, as is typical for an IC, the design layout includes several design layers.
After the arrangement of materials by layer is designed, a fabrication process is used to actually form material on each layer. That process includes a photo-lithographic process using a mask having opaque and transparent regions that causes light to fall on photosensitive material in a desired pattern. After light is shined through the mask onto the photosensitive material, the light-sensitive material is subjected to a developing process to remove those portions exposed to light (or, alternatively, remove those portions not exposed to light). Etching, deposition, diffusion, or some other material altering process is then performed on the patterned layer until a particular material is formed with the desired pattern in the particular layer. The result of the process is some arrangement of material in each of one or more layers, here called printed features layers.
Because of the characteristics of light in photolithographic equipment, and because of the properties of the material altering processes employed, the pattern of transparent and opaque areas on the mask is not the same as the pattern of materials on the printed layer. A mask design process is used, therefore, after the physical EDA process and before the fabrication process, to generate one or more mask layouts that differ from the design layers. When formed into one or more masks and used in a set of photolithographic processes and material altering processes, these mask layouts produce a printed features layer as close as possible to the design layer.
The particular size of a feature that a design calls for is the feature's critical dimension. The resolution for the fabrication process corresponds to the minimum sized feature that the photolithographic process and the material processes can repeatably form on a substrate, such as a silicon wafer. As the critical dimensions of the features on the design layers become smaller and approach the resolution of the fabrication process, the consistency between the mask and the printed features layer is significantly reduced. Specifically, it is observed that differences in the pattern of printed features from the mask depend upon the size and shape of the features on the mask and the proximity of the features to one another on the mask. Such differences are called proximity effects.
Some causes of proximity effects are optical proximity effects, such as diffraction of light through the apertures of the optical systems and the patterns of circuits that resemble optical gratings. Optical proximity effects also include underexposure of concave corners (inside corners with interior angles greater than 180 degrees) and overexposure of convex corners (outside corners with interior angles less than 180 degrees), where the polygon represents opaque regions, and different exposures of small features compared to large features projected from the same mask. Other causes of proximity effects are non-optical proximity effects, such as sensitivity of feature size and shape to angle of attack from etching plasmas or deposition by sputtering during the material altering processes, which cause features to have shapes and sizes that have decayed from or accumulated onto their designed shapes and sizes.
In attempts to compensate for proximity effects, the mask layouts can be modified. To illustrate,
FIG. 1A
shows mask items
170
, such as windows or opaque areas on a mask, represented by edges
171
on one or more polygons, and some printed features
180
with exaggerated proximity effects.
FIG. 1A
does not represent an actual example, but is provided simply to illustrate the concepts of proximity effects and mask modifications to attempt to correct for proximity effects. To make apparent the illustrated proximity effects, the projection of the original polygons
171
is shown as a fine line around the printed features
180
. Note that the printed features
180
includes a spurious connection feature
182
, an edge
185
entirely displaced inside the corresponding edge of the original outline
171
, and an end line
183
completely inside the outline of the original items
171
.
FIG. 1B
illustrates various ways mask items
190
are modified to correct for such effects.
FIG. 1B
is not a particular example of a particular set of corrections that actually mitigate the proximity effects illustrated in FIG.
1
A. The corrections available include hammerheads
192
(i.e. hammerheads
192
a
and
192
b
) added to ends of items to compensate for overexposure of the entire end line of a feature. Also shown are biases
196
(i.e. biases
196
a
and
196
b
) applied along portions of a straight edge of a feature. A negative bias like
196
represents a portion of an opaque area made transparent (or a portion of a window made opaque). In this case the negative bias reduces the size of the item on a mask to avoid generating the spurious feature
182
of FIG.
1
A. Also shown are assist features
194
(i.e. assist features
194
a
and
194
b
), which are separate items smaller than the resolution of the photolithographic process and thus too small to be formed in a photoresist layer, but which are sufficiently large to effect diffraction patterns that influence larger nearby features. The assist features
194
are intended to move the edge
185
of the printed features
180
in
FIG. 1A
toward the outline
171
of the original mask items
170
. Also shown is a sub-resolution serif
193
of extra opaque material to compensate for overexposure at convex corners of opaque areas, and an anti-serif
197
indicating where opaque material, if any, is removed to compensate for underexposure at concave corners of opaque polygons. These corrections are listed to illustrate the concepts of correcting a mask to compensate for proximity effects. The illustrated corrections do not necessarily correct the depicted features.
In rule-based proximity corrections, corrections such as the serifs and biases of a predetermined size are automatically placed at corners and edges of fabrication layout shapes like the mask shapes
170
. Other rules may include adding assist shapes to a mask near desired features from the design layout and adding hammerheads to short end lines of the desired features. Experience of engineers accumulated through trial and error can be expressed as rules, and applied during the fabrication design process. For example, a rule may be expressed as follows: if a feature is isolated, then widen the opaque region in the mask by a particular amount to compensate for expected overexposure, so that the feature prints properly.
The experience captured in rule-based corrections is garnered by going through the fabrication process repeatedly with different mask layouts, making adjustments and observing the results. However, this process consumes time and manufacturing capacity. Even if such experimental, rule-forming runs are made,
Pierrat Christophe
Zhang Youping
Bever Hoffman & Harms LLP
Harms Jeanette S.
Numerical Technologies Inc.
Pert Evan
Smith Matthew
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