Selection circuit and packet processing apparatus

Details Selection circuit and packet processing apparatus Selection circuit and packet processing apparatus

2009-07-23

2011-10-04

Spittle, Matthew D (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S240000, C710S200000

Reexamination Certificate

active

08032677

ABSTRACT:
An aspect of the embodiment utilizes a selection circuit that includes a first storage circuit for storing information of m×n bits each corresponding to a choice. The storage circuit indicates whether the corresponding choice is in a selectable state or not. A first round robin circuit for executing a round robin process on the second storage circuit selects one of the bits contained in the corresponding bit string and indicates that a choice is in a selectable state. A second round robin circuit executes the round robin process on the bit string having the m-bit width to select one of the bits indicating that the corresponding choice, and a control circuit controls the first and the second round robin circuit.

REFERENCES:
patent: 6665760 (2003-12-01), Dotson
patent: 2002/0178311 (2002-11-01), Liu et al.
patent: 2003-179632 (2003-06-01), None

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