Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output command process
Reexamination Certificate
2002-02-27
2004-04-13
Park, Ilwoo (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output command process
C710S005000, C710S036000, C710S039000, C710S040000, C710S240000, C710S244000
Reexamination Certificate
active
06721816
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to computer system input/output (I/O) and, more particularly, to transaction handling within an I/O node.
2. Description of the Related Art
In a typical computer system, one or more processors may communicate with input/output (I/O) devices over one or more buses. In addition those processors may communicate with each other through an additional bus or buses. In many cases, these buses are shared buses.
Unfortunately, many shared bus systems suffer from drawbacks. For example, multiple devices attached to a bus may present a relatively large electrical capacitance to devices driving signals on the bus. In addition, the multiple attach points on a shared bus produce signal reflections at high signal frequencies which reduce signal integrity. As a result, signal frequencies on the bus are generally kept relatively low in order to maintain signal integrity at an acceptable level. The relatively low signal frequencies reduce signal bandwidth, limiting the performance of devices attached to the bus.
Lack of scalability to larger numbers of devices is another disadvantage of shared bus systems. The available bandwidth of a shared bus is substantially fixed (and may decrease if adding additional devices causes a reduction in signal frequencies upon the bus). Once the bandwidth requirements of the devices attached to the bus (either directly or indirectly) exceeds the available bandwidth of the bus, devices will frequently be stalled when attempting access to the bus, and overall performance of the computer system including the shared bus will most likely be reduced. An example of a shared bus used by many systems is a front side bus (FSB), which may typically interconnect one or more processors and a system controller.
To overcome some of the drawbacks of a shared bus, some computers systems may use packet-based communications such as point-to-point links, for example, between devices or nodes. In such systems, nodes may communicate with each other by exchanging packets of information. In general, a “node” is a device which is capable of participating in transactions upon an interconnect. For example, the interconnect may be packet-based, and the node may be configured to receive and transmit packets. Generally speaking, a “packet” is a communication between two nodes: an initiating or “source” node which transmits the packet and a destination or “target” node which receives the packet. When a packet reaches the target node, the target node accepts the information conveyed by the packet and processes the information internally. A node located on a communication path between the source and target nodes may relay or forward the packet from the source node to the target node.
Many I/O bridging devices use a buffering mechanism to buffer a number of pending transactions from a peripheral bus to a final destination bus. However buffering may introduce stalls on the peripheral bus. Stalls may be caused when a series of transactions are buffered in a queue and awaiting transmission to a destination bus and a stall occurs on the destination bus, which stops forward progress. Then a transaction that will allow those waiting transactions to complete arrives at the queue and is stored behind the other transactions. To break the stall, the transactions in the queue must somehow be reordered to allow the newly arrived transaction to be transmitted ahead of the pending transactions. Thus to prevent scenarios such as this, peripheral buses such as the PCI bus prescribe a set of ordering rules that govern the handling and ordering of PCI bus transactions.
In nodes that bridge transactions having a set of ordering rules from one type of bus to a different bus such as a packet bus, the packet bus may also need to constrain the transactions to the same or a similar set of ordering rules. When these nodes buffer the transactions, an arbitration mechanism may select winning transactions while allowing the buffered transactions to be reordered. Depending on the complexity of the ordering rules, particularly between transactions having different origins, performance may be effected.
SUMMARY OF THE INVENTION
Various embodiments of an arbitration mechanism for an input/output node of a computer system are disclosed. In one embodiment, an arbitration mechanism includes a buffer circuit for storing received control commands within a first and second buffer. The first buffer may correspond to a posted virtual channel and the second buffer may correspond to a second virtual channel. Each of the control commands corresponds to one of the virtual channels and includes an identifier value. The identifier value may be indicative of the source of the control command. The mechanism also includes a tag circuit that is coupled to the buffer circuit and may generate a tag value for each of the control commands prior to the control commands being stored within the buffer circuit. The tag value may be indicative of an order of receipt of each of the control commands relative to other control commands and may be dependent upon the identifier value. In addition, the mechanism includes an arbitration circuit that may arbitrate between control commands stored within the first buffer and the second buffer dependent upon the tag value of each of the control commands. However, during arbitration, each control command belonging to the second virtual channel may further include a flag bit which indicates that the arbitration circuit may select, independently of the tag values, a given control command having the flag bit set.
In one particular implementation, the tag circuit may compare the identifier values of the control commands stored within the first buffer to the identifier value of each of the control commands belonging to the second virtual channel that is received.
In another implementation, the tag circuit may set the flag bit if the identifier value of the given one of the control commands is different than the identifier values of the posted control commands stored within the first buffer.
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U.S. patent application Ser. No. 09/399,281, filed Sep. 17, 1999.
Ennis Stephen C.
Magro James R.
Advanced Micro Devices , Inc.
Kivlin B. Noäl
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Park Ilwoo
LandOfFree
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