Selectable width, brustable FIFO

Details Selectable width, brustable FIFO Selectable width, brustable FIFO

1991-09-10

1995-11-21

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Serial read/write

365 73, G11C 1300

Patent

active

054693985

ABSTRACT:
A selectable width, burstable FIFO is described. A register memory stores x-bit and y-bit data. Each register of the register memory is y+1 bits wide. Y bits store x-bit and y-bit data and 1-bit tracks the data width within each register. A Burst Ready Logic means accepts an m-bit input to select a burst length from 2.sup.m possible burst lengths. Based on the m-bit input, the Burst Ready Logic outputs a signal indicating when the FIFO is burstable. The empty and full FIFO conditions are determined using a digital hysteresis. In one embodiment, the FIFO is used in an IBM-AT environment. Eight registers store 8-bit and 16-bit data. Each register is 17-bits wide so that 16-bits store 8-bit and 16-bit data. The remaining bit tracks whether the register contains 8-bit or 16-bit data. In this embodiment, the Burst Ready Logic accepts a 2-bit input to select from possible burst lengths of 1, 2, 4 or 8 bytes.

REFERENCES:
patent: 3763480 (1973-10-01), Weimer

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